Altera Video and Image Processing Suite - Manual (Page 248)

Test Pattern Generator Signals
Table 19-4: Test Pattern Generator Signals
Signal Direction Description
reset
Input The IP core asynchronously resets when you assert this
signal. You must deassert this signal synchronously to the
rising edge of the clock signal.
clock
Input The main system clock. The IP core operates on the rising
edge of this signal.
control_av_address
Input
control
slave port Avalon-MM address bus. Specifies a
word offset into the slave address space.
Note: Present only if you turn on Run-time control
of image size..
control_av_chipselect
Input
control
slave port Avalon-MM chip select signal. When
you assert this signal, the
control
port ignores all other
signals unless you assert this signal.
Note: Present only if you turn on Run-time control
of image size..
control_av_readdata
Output
control
slave port Avalon-MM read data bus. These
output lines are used for read transfers.
Note: Present only if you turn on Run-time control
of image size..
control_av_write
Input
control
slave port Avalon-MM
write
signal. When you
assert this signal, the
control
port accepts new data from
the write data bus.
Note: Present only if you turn on Run-time control
of image size..
control_av_writedata
Input
control
slave port Avalon-MM write data bus. These
input lines are used for write transfers.
Note: Present only if you turn on Run-time control
of image size..
dout_data
Output
dout
port Avalon-ST
data
bus. This bus enables the
transfer of pixel data out of the IP core.
dout_endofpacket
Output
dout
port Avalon-ST
endofpacket
signal. This signal
marks the end of an Avalon-ST packet.
dout_ready
Input
dout
port Avalon-ST
ready
signal. The downstream
device asserts this signal when it is able to receive data.
19-6 Test Pattern Generator Signals
UG-VIPSUITE
2015.05.04
Altera Corporation Test Pattern Generator IP Cores
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