Altera Video and Image Processing Suite - Manual (Page 84)

Parameter Value Description
Separate syncs only - Frame/
Field 1: Vertical back porch
32–65536, Default = 36 Specify the number of lines in the vertical
back porch in pixels for Frame/Field 1.
Interlaced and Field 0: F rising
edge line
32–65536, Default = 0 Specify the line when the rising edge of the
field bit occurs for Interlaced and Field 0.
Interlaced and Field 0: F falling
edge line
32–65536, Default = 0 Specify the line when the falling edge of the
field bit occurs for Interlaced and Field 0.
Interlaced and Field 0: Vertical
blanking rising edge line
32–65536, Default = 0 Specify the line when the rising edge of the
vertical blanking bit for Field 0 occurs for
Interlaced and Field 0.
Interlaced and Field 0: Ancillary
packet insertion line
32–65536, Default = 0 Specify the line where ancillary packet
insertion starts.
Embedded syncs only - Field 0:
Vertical blanking
32–65536, Default = 0 Specify the size of the vertical blanking period
in pixels for Interlaced and Field 0.
Separate syncs only - Field 0:
Vertical sync
32–65536, Default = 0 Specify the number of lines in the vertical
synchronization period for Interlaced and
Field 0.
Separate syncs only - Field 0:
Vertical front porch
32–65536, Default = 0 Specify the number of lines in the vertical
front porch period for Interlaced and Field 0.
Separate syncs only - Field 0:
Vertical back porch
32–65536, Default = 0 Specify the number of lines in the vertical
back porch period for Interlaced and Field 0.
Pixel FIFO size 32–(memory limit),
Default = 1920
Specify the required FIFO depth in pixels,
(limited by the available on-chip memory).
FIFO level at which to start
output
0–(memory limit),
Default = 1919
Specify the fill level that the FIFO must have
reached before the output video starts.
Video in and out use the same
clock
On or Off Turn on if you want to use the same signal for
the input and output video image stream
clocks.
Use control port On or Off Turn on to use the optional Avalon-MM
control port.
Accept synchronization outputs On or Off Turn on to use the synchronization outputs
(
sof
,
sof_locked
) from the CVI IP cores.
Run-time configurable video
modes
1–14, Default = 1 Specify the number of run-time configurable
video output modes that are required when
you are using the Avalon-MM control port.
Note: This parameter is available only
when you turn on Use control
port.
Width of vid_std bus 1–16, Default = 1 Select the width of the
vid_std
bus, in bits.
UG-VIPSUITE
2015.05.04
Clocked Video Interface Parameter Settings 4-25
Clocked Video Interface IP Cores Altera Corporation
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