Altera Video and Image Processing Suite - Manual (Page 209)

Signal Direction Description
mem_reset
Input
mem_master
port
reset
signal. The interface asynchro‐
nously resets when this signal is high. You must deassert
this signal synchronously to the rising edge of the
clock
signal.
din_data
Input
din
port Avalon-ST
data
bus. This bus enables the
transfer of pixel data into the IP core.
din_endofpacket
Input
din
port Avalon-ST
endofpacket
signal. This signal
marks the end of an Avalon-ST packet.
din_ready
Output
din
port Avalon-ST
ready
signal. This signal indicates
when the IP core is ready to receive data.
din_startofpacket
Input
din
port Avalon-ST
startofpacket
signal. This signal
marks the start of an Avalon-ST packet.
din_valid
Input
din
port Avalon-ST
valid
signal. This signal identifies the
cycles when the port must enter data.
dout_data
Output
dout
port Avalon-ST
data
bus. This bus enables the
transfer of pixel data out of the IP core.
dout_endofpacket
Output
dout
port Avalon-ST
endofpacket
signal. This signal
marks the end of an Avalon-ST packet.
dout_ready
Input
dout
port Avalon-ST
ready
signal. The downstream
device asserts this signal when it is able to receive data.
dout_startofpacket
Output
dout
port Avalon-ST
startofpacket
signal. This signal
marks the start of an Avalon-ST packet.
dout_valid
Output
dout
port Avalon-ST
valid
signal. The IP core asserts this
signal when it produces data.
mem_master_rd_address
Output
mem_master_rd
port Avalon-MM
address
bus. This bus
specifies a byte address in the Avalon-MM address space.
mem_master_rd_burstcount
Output
mem_master_rd
port Avalon-MM
burstcount
signal.
This signal specifies the number of transfers in each burst.
mem_master_rd_read
Output
mem_master_rd
port Avalon-MM
read
signal. The IP core
asserts this signal to indicate read requests from the
master to the system interconnect fabric.
mem_master_rd_readdata
Input
mem_master_rd
port Avalon-MM
readdata
bus. These
input lines carry data for read transfers.
mem_master_rd_readdatavalid
Input
read_master
port Avalon-MM
readdatavalid
signal.
The system interconnect fabric asserts this signal when the
requested read data has arrived.
mem_master_rd_waitrequest
Input
mem_master_rd
port Avalon-MM
waitrequest
signal.
The system interconnect fabric asserts this signal to cause
the master port to wait.
14-12 Frame Buffer Signals
UG-VIPSUITE
2015.05.04
Altera Corporation Frame Buffer IP Cores
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