Altera Video and Image Processing Suite - Manual (Page 226)

• N
v
= vertical taps
• N
h
= horizontal taps
• B
data
= bit width of the data samples
• B
v
= bit width of the vertical coefficients
• B
h
= bit width of the horizontal coefficients
• P
v
= user-defined number of vertical phases for each coefficient set (must be a power of 2)
• P
h
= user-defined number of horizontal phases for each coefficient set (must be a power of 2)
• C
v
= number of vertical coefficient banks
• C
h
= number of horizontal coefficient banks
The total number of multipliers is N
v
+ N
h
per channel in parallel.
The width of each vertical multiplier is max(B
data
, B
v
)
The width of each horizontal multiplier is the maximum of the horizontal coefficient width, B
h,
and the
bit width of the horizontal kernel, B
kh
.
The bit width of the horizontal kernel determines the precision of the results of vertical filtering and is
user-configurable.
The memory requirement is N
v
line-buffers plus vertical and horizontal coefficient banks. As in the
nearest-neighbor and bilinear methods, each line buffer is the same size as one line from the clipped input
image.
The vertical coefficient banks are stored in memory that is B
v
bits wide and P
v
×N
v
×C
v
words deep. The
horizontal coefficient banks are stored in memory that is B
h
×N
h
bits wide and P
h
×C
h
words deep. For
each coefficient type, the Quartus II software maps these appropriately to physical on-chip RAM or logic
elements as constrained by the width and depth requirements.
Note: If the horizontal and vertical coefficients are identical, they are stored in the horizontal memory (as
defined above). If you turn on Share horizontal /vertical coefficients in the parameter editor, this
setting is forced even when the coefficients are loaded at run time.
Double-Buffering
Using multiple coefficient banks allows double-buffering, fast swapping, or direct writing to the scaler’s
coefficient memories. he coefficient bank to be read during video data processing and the bank to be
written by the Avalon-MM interface are specified separately at run time.
Choosing to have more memory banks allows for each bank to contain coefficients for a specific scaling
ratio and for coefficient changes to be accomplished very quickly by changing the read bank. Alterna‐
tively, for memory-sensitive applications, use a single bank and coefficient writes have an immediate
effect on data processing.
To accomplish double-buffering:
1. Select two memory banks at compile time.
2. At start-up run time, select a bank to write into (for example 0) and write the coefficients.
3. Set the chosen bank (0) to be the read bank for the Scaler II IP core, and start processing.
4. For subsequent changes, write to the unused bank (1) and swap the read and write banks between
frames.
UG-VIPSUITE
2015.05.04
Double-Buffering 17-5
Scaler II IP Core Altera Corporation
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