Altera Video and Image Processing Suite - Manual (Page 88)

Signal Direction Description
vid_hd_sdn
Input Clocked video color plane format selection signal. This
signal distinguishes between sequential (when low) and
parallel (when high) color plane formats.
Note: For run-time switching of color plane
transmission formats mode only.
vid_v_sync
Input Clocked video vertical synchronization signal. Assert this
signal during the vertical synchronization period of the
video stream.
Note: For separate synchronization mode only.
vid_locked
Input Clocked video locked signal. Assert this signal when a
stable video stream is present on the input. Deassert this
signal when the video stream is removed.
CVO II IP core: When 0 this signal is used to reset the
vid_clk
clock domain registers, it is synchronized to the
vid_clk
internally so no external synchronization is
required.
vid_std
Input Video standard bus. Can be connected to the
rx_std
signal of the SDI IP core (or any other interface) to read
from the
Standard
register.
vid_de
Input This signal is asserted when you turn on Add data enable
signal. This signal indicates the active picture region of an
incoming line.
Table 4-17: Clocked Input II Signals
Signal Direction Description
main_reset_reset
Input The IP core asynchronously resets when you assert this
signal. You must deassert this signal synchronously to the
rising edge of the clock signal.
main_clock_clk
Input The main system clock. The IP core operates on the rising
edge of this signal.
dout_data
Output
dout
port Avalon-ST
data
bus. This bus enables the
transfer of pixel data out of the IP core.
dout_endofpacket
Output
dout
port Avalon-ST
endofpacket
signal. This signal is
asserted when the IP core is ending a frame.
dout_ready
Input
dout
port Avalon-ST
ready
signal. The downstream
device asserts this signal when it is able to receive data.
dout_startofpacket
Output
dout
port Avalon-ST
startofpacket
signal. This signal is
asserted when the IP core is starting a new frame.
UG-VIPSUITE
2015.05.04
Clocked Video Interface Signals 4-29
Clocked Video Interface IP Cores Altera Corporation
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