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6 real-time clock register locations, 4 operating system timer, Real-time clock register locations -21 – Intel STRONGARM SA-1100 User Manual

Page 91: Operating system timer -21

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SA-1100 Developer’s Manual

9-21

System Control Module

This trim setting leaves an error of .16 cycles per 1023 seconds. The error calculation yields (in
parts-per-million or ppm):

Maximum Error Calculation Versus Real-Time Clock Accuracy

As seen from trim example #2, the maximum possible error approaches 1 clock per 2

10

-1 seconds.

Calculating the ppm error for this scenario yields:

To maintain an accuracy of +/- 5 seconds per month, the required accuracy is calculated to be:

This calculation indicates that the accuracy of the SA-1100 trim mechanism is more than adequate
to compensate for the static environmental and manufacturing variables, and still provides
acceptable accuracy.

9.3.6

Real-Time Clock Register Locations

The following table describes the real-time clock registers.

9.4

Operating System Timer

The SA-1100 contains a 32-bit operating system timer that is clocked by the 3.6864-MHz oscillator.
The operating system count register (OSCR) is a free-running up-counter that is not cleared during
any reset (contains unknown value after reset). The OS timer also contains four 32-bit match registers
(OSMR<3:0>). Each register can be written and read by the user. When the value in the OSCR
matches (is equal to) the value within any of the match registers, and the interrupt enable bit is set, the
corresponding bit in the OSSR is set. These bits are also routed to the interrupt controller where they
can be programmed to cause an interrupt. OSMR<3> also serves as a watchdog match register that
resets the SA-1100 when a match occurs. The only register that is reset to a known state is the
watchdog match enable register (WMER). The user must initialize all other registers and clear any set
status bits before the FIQ and IRQ interrupts are enabled within the CPU.

Error

0.16 cycles

1023 sec

---------------------------

X

1 sec

32768 cycles

-------------------------------

0.002 ppm

=

=

Error (maximum)

1 cycle

1023 sec

---------------------

X

1 sec

32768 cycles

-------------------------------

0.03 ppm

=

=

Error

5 sec

month

---------------

X

1 month

2592000 sec

------------------------------

1.9 ppm

=

=

Address

Name

Description

0h 9001 0004

RCNR

RTC count register

0h 9001 0000

RTAR

RTC alarm register

0h 9001 0010

RTSR

RTC status register

0h 9001 0008

RTTR

RTC timer trim register