Intel STRONGARM SA-1100 - Manual (Page 65)

SA-1100 Developer’s Manual 7-3
Memory-Management Unit (MMU)
Note: Care must be taken if the translated address differs from the untranslated address because the three
instructions following the enabling of the MMU will have been fetched using “flat translation”,
and enabling the MMU may be considered a branch with delayed execution. A similar situation
occurs when the MMU is disabled. Consider the following code sequence:
To disable the MMU:
1. Disable the WB by clearing bit 3 in the control register.
2. Disable the Dcache by clearing bit 2 in the control register.
3. Disable the Icache by clearing bit 12 in the control register.
4. Disable the MMU by clearing bit 0 in the control register.
Note: If the MMU is disabled and subsequently reenabled, the contents of the TB is preserved. If the
contents are now invalid, the TB should be flushed before reenabling the MMU.
7.5 Mini Data Cache
The mini data cache is a 16-entry, 2-way set-associative data cache. It is accessed in parallel with
the main data cache. A data reference is allocated into the mini data cache if the B and C bits in
the MMU are 0 and 1, respectively. A line of data can reside only in one of the two Dcaches at any
one time. Both Dcaches must be flushed prior to any page table manipulation that could change the
allocation policy.
MOV R1, #0x1
MCR 15,0,R1,0,0 ; Enable MMU
Fetch nontranslated
Fetch nontranslated
Fetch nontranslated
Fetch Translated