Intel STRONGARM SA-1100 - Manual (Page 225)

SA-1100 Developer’s Manual 11-75
Peripheral Control Module
11.8.12 UDC Data Register
The UDC data register (UDDR) is an 8-bit register corresponding to both the top and bottom
entries of the transmit and receive FIFOs, respectively. Data is placed by the UDC’s receive logic
into the top of the receive FIFO. The data is transferred down the FIFO to the lowest location that
is empty. When UDDR is read, the bottom entry of the 8-bit receive FIFO is accessed. After the
read, the bottom FIFO entry is invalidated, which causes all data in the FIFO to automatically
transfer down one location.
When UDDR is written, the topmost FIFO entry of the 8-bit transmit FIFO is accessed. After a
write, the data is automatically transferred down the FIFO to the lowest location that is empty. The
UDC’s transmit logic takes 8-bit values from the bottom of the transmit FIFO one at a time, places
the data into a serial shifter, and transmits the value out onto the UDC pins. Each time a value is
taken from the bottom entry, the location is invalidated, which causes all data in the FIFO to
automatically transfer down one location.
The following table shows the location of the top/bottom of the transmit/receive FIFOs in the UDC
data register (UDDR). Note that both FIFOs are cleared when the SA-1100 is reset and when UDE
is written to zero. After either of these actions takes place, the user may prime the transmit FIFO by
writing up to sixteen 8-bit values to UDDR before enabling the UDC.
Address: 0h 8000 0008 UDDR Read/Write
Bit 7 6 5 4 3 2 1 0
Bottom of receive FIFO
Reset 0 0 0 0 0 0 0 0
Read Access
Bit 7 6 5 4 3 2 1 0
Top of transmit FIFO
Reset 0 0 0 0 0 0 0 0
Write Access
Bit Name Description
7..0 DATA Top/bottom of transmit/receive FIFO data.
Read – Bottom of receive FIFO data.
Write – Top of transmit FIFO data.