Intel STRONGARM SA-1100 - Manual (Page 12)

xii SA-1100 Developer’s Manual
11.10.10.4Transmit FIFO Service Request Flag (TFS)
(read-only, maskable interrupt).......................................... 11-122
11.10.10.5Receive FIFO Service Request Flag (RFS)
(read-only, maskable interrupt).......................................... 11-122
11.10.10.6Framing Error Status (FRE)
(read/write, nonmaskable interrupt) ................................... 11-123
11.10.11HSSP Status Register 1 ................................................................ 11-124
11.10.11.1Receiver Synchronized Flag (RSY)
(read-only, noninterruptible)............................................... 11-124
11.10.11.2Transmitter Busy Flag (TBY)
(read-only, noninterruptible)............................................... 11-124
11.10.11.3Receive FIFO Not Empty Flag (RNE)
(read-only, noninterruptible)............................................... 11-124
11.10.11.4Transmit FIFO Not Full Flag (TNF)
(read-only, noninterruptible)............................................... 11-124
11.10.11.5End-of-Frame Flag (EOF)
(read-only, noninterruptible)............................................... 11-124
11.10.11.6CRC Error Status (CRE)
(read-only, noninterruptible)............................................... 11-125
11.10.11.7Receiver Overrun Status (ROR)
(read-only, noninterruptible)............................................... 11-125
11.10.12UART Register Locations .............................................................. 11-127
11.10.13HSSP Register Locations .............................................................. 11-127
11.11 Serial Port 3 - UART .................................................................................... 11-128
11.11.1 UART Operation ............................................................................. 11-128
11.11.1.1Frame Format .................................................................. 11-129
11.11.1.2Baud Rate Generation ..................................................... 11-129
11.11.1.3Receive Operation ........................................................... 11-129
11.11.1.4Transmit Operation .......................................................... 11-130
11.11.1.5Transmit and Receive FIFOs........................................... 11-130
11.11.1.6CPU and DMA Register Access Sizes ............................ 11-131
11.11.2 UART Register Definitions.............................................................. 11-131
11.11.3 UART Control Register 0 ................................................................ 11-131
11.11.3.1Parity Enable (PE) ........................................................... 11-131
11.11.3.2Odd/Even Parity Select (OES) ........................................ 11-131
11.11.3.3Stop Bit Select (SBS) ...................................................... 11-132
11.11.3.4Data Size Select (DSS) ................................................... 11-132
11.11.3.5Sample Clock Enable (SCE) ........................................... 11-132
11.11.3.6Receive Clock Edge Select (RCE) .................................. 11-132
11.11.3.7Transmit Clock Edge Select (TCE).................................. 11-133
11.11.4 UART Control Registers 1 and 2 .................................................... 11-134
11.11.4.1Baud Rate Divisor (BRD)................................................. 11-134
11.11.5 UART Control Register 3 ................................................................ 11-135
11.11.5.1Receiver Enable (RXE) ................................................... 11-135
11.11.5.2Transmitter Enable (TXE) ................................................ 11-135
11.11.5.3Break (BRK) .................................................................... 11-135
11.11.5.4Receive FIFO Interrupt Enable (RIE)............................... 11-135
11.11.5.5Transmit FIFO Interrupt Enable (TIE) .............................. 11-136
11.11.5.6Loopback Mode (LBM) .................................................... 11-136
11.11.6 UART Data Register ....................................................................... 11-137
11.11.7 UART Status Register 0 ................................................................. 11-139
11.11.7.1Transmit FIFO Service Request Flag (TFS)
(read-only, maskable interrupt).......................................... 11-139