Intel STRONGARM SA-1100 - Manual (Page 334)

11-184 SA-1100 Developer’s Manual
Peripheral Control Module
11.13 Peripheral Pin Controller (PPC)
The peripheral pin controller (PPC) takes individual control of the LCD’s and serial port 1..4’s pins
when one or more of the units are disabled, allowing the user to utilize them as general-purpose
digital I/O pins to communicate to off-chip resources. When controlled by the PPC, peripheral
control module (PCM) pins operate similarly to GPIO pins except that they cannot perform edge
detection and interrupt generation. The PPC is also used to specify the direction of the peripherals’
pins when sleep mode is entered.
Note that serial ports 1..3 contain individual enables for their transmit and receive serial engines.
Thus, if only half-duplex transmission is needed, one pin can be used for serial communication and
the other for digital I/O communication. Also note that serial port 0’s pins are dedicated to the USB
device controller (UDC), which uses the pins to drive a differential transceiver, preventing them
from being used as digital I/O pins when the UDC is disabled.
11.13.1 PPC Operation
Following a hardware reset of the SA-1100 (nRESET asserted then negated), all peripheral control
module units are disabled, giving control of their pins to the PPC (except serial port 0). The PPC, in
turn, configures all peripheral pins it controls as inputs. Once reset is negated, the user should
program the peripherals as soon as possible, and configure the pins of any peripheral that is not
usable to function as general-purpose I/O signals. This should be done quickly to limit the amount
of power consumed at startup because pins that are intended to function as outputs within the
system are initially configured as inputs, and the receiving device to which they are connected will
float and consume power.
The PPC contains special resources to limit off-chip power consumption during and immediately
following the assertion of sleep mode. The PPC contains a sleep mode direction register, which is
programmed by the user, and individually configures 22 of the peripherals’ pins either as inputs or
outputs during sleep mode. When configured as an output, the pin is forced low in sleep mode. This
special register is required because the first action taken when sleep mode is entered is the assertion
of reset to all the peripherals, which would, in turn, errantly configure all peripheral pins as inputs.
The sleep mode direction register is not reset; the user can maintain the correct direction
programmed for each of the peripherals’ pins while in sleep mode. When sleep mode is exited, the
user can then reprogram the peripherals and the PPC registers to resume control of the peripherals’
pins. To keep the same pin direction and state after sleep mode has been negated but before the user
reprograms the peripherals, the system control module’s power manager maintains the peripherals’
pin direction and state following sleep negation until the peripheral control hold bit (PSSR:PH),
located in the power manager, is cleared (by writing a one to it). Therefore, the pin direction and
state established during sleep using the sleep mode direction register remains intact following the
negation of sleep until the PH bit is cleared. Once PH is cleared, control of the peripherals’ pins is
given back to the individual peripherals and to the PPC unit.
Most of the SA-1100’s peripherals can take control of one or more GPIO pins (which are normally
controlled within the system control module) to act as input or output triggers, or to drive or supply
clocks to the peripherals. The GPIO unit contains a GPIO alternate function register (GAFR) that
the user must program to give control of the GPIO pins to the individual peripheral units for each
of the alternate functions. The user must also program the GPIO pin direction register (GPDR) for
the corresponding pins that are used by the peripheral units. The GPIO pin alternate functions are
then enabled within the individual peripherals using a control bit. However, two control bits exist
within the PPC that configure six of the GPIO unit’s pins for peripheral alternate functions.