Intel STRONGARM SA-1100 - Manual (Page 232)

11-82 SA-1100 Developer’s Manual
Peripheral Control Module
11.9.1.8 Receive Operation
Once the SDLC receiver is enabled, it enters hunt mode, searching the incoming data stream for the
flag (01111110). The flag serves to achieve bit synchronization, denotes the beginning of a frame,
and delineates the boundaries of individual bytes of data. The end of the flag denotes the beginning
of the address byte. Once the flag is found, the receiver is synchronized to incoming data and hunt
mode is exited.
After each bit is decoded, a serial shifter is used to receive the incoming data a byte at a time. Once
the flag is recognized, each subsequent byte of data is decoded and placed within a 2-byte
temporary FIFO. A temporary FIFO is used to prevent the CRC from being placed within the
receive FIFO. When the temporary FIFO is filled, data values are pushed out one by one to the
receive FIFO. The first byte of a frame is the address. If receiver address matching is enabled, the
received address is compared to the address programmed in the address match value field in a
control register. If the two values are equal or if the incoming address contains all ones, all
subsequent data bytes including the address byte are stored in the receive FIFO. If the values do not
match, the receive logic does not store any data in the receive FIFO, ignores the remainder of the
frame, and begins to search for the stop flag. The second byte of the frame can contain an optional
control field, which must be decoded in software (no hardware support within the SDLC). Use of a
control byte is determined by the user.
When the receive FIFO is one- to two-thirds full, an interrupt and/or DMA request is signalled. If
the data is not removed soon enough, and the FIFO is completely filled, an overrun error is
generated when the receive logic attempts to place additional data into the full FIFO. Once the
FIFO is full, all subsequent data bytes received are lost while all FIFO contents remain intact.
Frames can contain any amount of data in multiples of 8 bits. Although the SDLC protocol does
not limit frame size, in practice they tend to be implemented in numbers ranging from hundreds to
thousands of bytes.
The receive logic continuously searches for the stop flag at the end of the frame. Once it is
recognized, the last byte that was placed within the receive FIFO is flagged as the last byte of the
frame, and the two bytes remaining within the temporary FIFO are removed and used as the 16-bit
CRC value for the frame. Instead of placing this in the receive FIFO, the receive logic compares it
to the CRC-CCITT value, which is continuously calculated using the incoming data stream. If they
do not match, the last byte that was placed within the receive FIFO is also flagged with a CRC
error. The CRC value is not placed in the receive FIFO.
The SDLC protocol permits back-to-back frames to be received. When this occurs, the flag at the
end of the first frame also serves as the flag to denote the beginning of the next frame (only one
flag separates the two). Most commercial SCCs continuously transmit flags between frames when
they do not occur back-to-back. To support both of these cases, the receive logic allows one or
more flags to separate frames. When the use of two start flags is programmed by the user, two flags
always separate back-to-back frames that are transmitted.
Most commercial SCCs can generate an abort (7 to 13 ones) when their transmit FIFO underruns.
The receive logic contains a counter that increments each time a one is decoded before entering the
serial shifter and is reset any time a zero is decoded. When seven or more ones are detected, a
receiver abort occurs. Note that data is moved from the serial shifter to the temporary FIFO a byte
at a time, and seven consecutive ones may bridge two bytes. For this reason, after an abort is
detected, the remaining data in the serial shifter is discarded along with the most recent byte of data
placed in the temporary FIFO. After this data is discarded, the oldest byte of data in the temporary
FIFO is placed in the receive FIFO, the EOF tag is set within the top entry of the FIFO (next to the
byte transferred from the temporary FIFO), the receiver abort interrupt is signalled, and the
receiver logic enters hunt mode until it recognizes the next flag.