Intel STRONGARM SA-1100 - Manual (Page 277)

SA-1100 Developer’s Manual 11-127
Peripheral Control Module
11.10.12 UART Register Locations
Table 11-16 shows the registers associated with the UART block and the physical addresses used to
access them.
11.10.13 HSSP Register Locations
Table 11-17 shows the registers associated with the HSSP block and the physical addresses used to
access them.
Table 11-16. UART Control, Data, and Status Register Locations
Address Name Description
0h 8003 0000 UTCR0 UART control register 0
0h 8003 0004 UTCR1 UART control register 1
0h 8003 0008 UTCR2 UART control register 2
0h 8003 000C UTCR3 UART control register 3
0h 8003 0010 UTCR4 UART control register 4
0h 8003 0014 UTDR UART data register
0h 8003 0018 — Reserved
0h 8003 001C UTSR0 UART status register 0
0h 8003 0020 UTSR1 UART status register 1
0h 8003 0024 –
0h 8003 005C
— Reserved
Table 11-17. HSSP Control, Data, and Status Register Locations
Address Name Description
0h 8004 0060 HSCR0 HSSP control register 0
0h 8004 0064 HSCR1 HSSP control register 1
0h 8004 0068 — Reserved
0h 8004 006C HSDR HSSP data register
0h 8004 0070 — Reserved
0h 8004 0074 HSSR0 HSSP status register 0
0h 8004 0078 HSSR1 HSSP status register 1
0h 8004 007C - 0h 8004 FFFF — Reserved
Note: HSCR2 resides within the same address space as the PPC.
0h 9006 0028 HSCR2 HSSP Control register 2