Intel STRONGARM SA-1100 User Manual
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SA-1100 Developer’s Manual
11.7.5.1Lines Per Panel (LPP) ......................................................... 11-36
11.7.5.2Vertical Sync Pulse Width (VSW) ........................................ 11-36
11.7.5.3End-of-Frame Line Clock Wait Count (EFW)....................... 11-37
11.7.5.4Beginning-of-Frame Line Clock Wait Count (BFW) ............. 11-37
11.7.6 LCD Controller Control Register 3 .................................................... 11-39
11.7.6.1Pixel Clock Divider (PCD).................................................... 11-39
11.7.6.2AC Bias Pin Frequency (ACB)............................................. 11-39
11.7.6.3AC Bias Pin Transitions Per Interrupt (API)......................... 11-40
11.7.6.4Vertical Sync Polarity (VSP) ................................................ 11-40
11.7.6.5Horizontal Sync Polarity (HSP)............................................ 11-40
11.7.6.6Pixel Clock Polarity (PCP) ................................................... 11-40
11.7.6.7Output Enable Polarity (OEP).............................................. 11-41
11.7.7 LCD Controller DMA Registers......................................................... 11-42
11.7.8 DMA Channel 1 Base Address Register........................................... 11-43
11.7.9 DMA Channel 1 Current Address Register....................................... 11-44
11.7.10 DMA Channel 2 Base and Current Address Registers..................... 11-45
11.7.11 LCD Controller Status Register ........................................................ 11-46
11.7.11.1LCD Disable Done Flag (LDD)
(read/write, maskable interrupt) ........................................... 11-46
11.7.11.2Base Address Update Flag (BAU)
(read-only, maskable interrupt)............................................ 11-46
11.7.11.3Bus Error Status (BER)
(read/write, maskable interrupt) ........................................... 11-46
11.7.11.4AC Bias Count Status (ABC)
(read/write, nonmaskable interrupt) ..................................... 11-47
11.7.11.5Input FIFO Overrun Lower Panel Status (IOL)
(read/write, maskable interrupt) ........................................... 11-47
11.7.11.6Input FIFO Underrun Lower Panel Status (IUL)
(read/write, maskable interrupt) ........................................... 11-47
11.7.11.7Input FIFO Overrun Upper Panel Status (IOU)
(read/write, maskable interrupt) ........................................... 11-47
11.7.11.8Input FIFO Underrun Upper Panel Status (IUU)
(read/write, maskable interrupt) ........................................... 11-47
11.7.11.9Output FIFO Overrun Lower Panel Status (OOL)
(read/write, maskable interrupt) ........................................... 11-47
11.7.11.10Output FIFO Underrun Lower Panel Status (OUL)
(read/write, maskable interrupt) ........................................... 11-48
11.7.11.11Output FIFO Overrun Upper Panel Status (OOU)
(read/write, maskable interrupt) ........................................... 11-48
11.7.11.12Output FIFO Underrun Upper Panel Status (OUU)
(read/write, maskable interrupt) ........................................... 11-48
11.7.12 LCD Controller Register Locations ................................................... 11-50
11.7.13 LCD Controller Pin Timing Diagrams................................................ 11-51
11.8.1.1Signalling Levels.................................................................. 11-57
11.8.1.2Bit Encoding ........................................................................ 11-58
11.8.1.3Field Formats....................................................................... 11-59
11.8.1.4Packet Formats ................................................................... 11-60
11.8.1.5Transaction Formats............................................................ 11-61
11.8.1.6UDC Device Requests......................................................... 11-62
11.8.2 UDC Register Definitions.................................................................. 11-63
11.8.3 UDC Control Register ....................................................................... 11-64