Intel STRONGARM SA-1100 - Manual (Page 244)

11-94 SA-1100 Developer’s Manual
Peripheral Control Module
11.9.7 SDLC Data Register
The SDLC data register (SDDR) is an 8-bit register corresponding to both the top and bottom
entries of the transmit and receive FIFOs, respectively.
When SDDR is read, the lower 8 bits of the bottom entry of the 11-bit receive FIFO is accessed. As
data enters the top of the receive FIFO, bits 8..10 are used as tags to indicate various conditions that
occur during reception of each piece of data. The tag bits are transferred down the FIFO along with
the data byte that encountered the condition. When data reaches the bottom, bit 8 of the bottom
FIFO entry is automatically transferred to the end of frame (EOF) flag, bit 9 to the CRC error
(CRE) flag, and bit 10 to the receiver overrun (ROR) flag, all within SDLC status register 1. The
user can read these flags to determine if the value at the bottom of the FIFO represents the last byte
within the packet and/or encountered an error during reception. After checking the flags, the FIFO
value can then be read, which causes the data in the next location of the receive FIFO to
automatically transfer down to the bottom entry and its EOF/CRE/ROR bits to be transferred to the
status register.
The end/error in FIFO (EIF) status bit is set within status register 0 whenever one or more of the
tag bits (8..10) are set within any of the bottom four entries of the receive FIFO and is cleared when
no error bits are set in the bottom four entries of the FIFO. When EIF is set, an interrupt is
generated and receive FIFO DMA requests are disabled so that the user can manually empty FIFO,
always checking the end of frame, CRC error, and overrun error flags in status register 1 first
before removing each data value from the FIFO. After each entry is removed, the user should
check the EIF bit to see if any errors remain, and repeat the procedure until all errors are flushed
from the FIFO. Once EIF is cleared, servicing of the receive FIFO by the DMA controller is
automatically reenabled.
When SDDR is written, the topmost entry of the 8-bit transmit FIFO is accessed. After a write, data
is automatically transferred down to the lowest location within the transmit FIFO, which does not
already contain valid data. Data is removed from the bottom of the FIFO one piece at a time by the
transmit logic, is loaded into the transmit serial shifter, and is then serially shifted out onto the
TXD1 pin at the programmed baud rate.