Intel STRONGARM SA-1100 - Manual (Page 201)

SA-1100 Developer’s Manual 11-51
Peripheral Control Module
11.7.13 LCD Controller Pin Timing Diagrams
Figure 11-10. Passive Mode Beginning-of-Frame Timing
A4790-01
L_FCLK
L_LCLK
L_PCLK
LDD[x:0]
Notes:
LEN - LCD enable:
0 - LCD is disabled.
1 - LCD is enabled.
VSP - Vertical sync polarity:
0 - Frame clock is active high, inactive low.
1 - Frame clock is active low, inactive high.
VSW - Vertical Sync Pulse Width:
1 to 64 horizontal sync clock periods to assert the vertical sync signal (hsync transitions).
HSP - Horizontal sync polarity:
0 - Line clock is active high, inactive low.
1 - Line clock is active low, inactive high.
ELW - End-of-line pixel clock wait count:
1 to 256 "dummy" pixel clock periods to wait after last pixel in line before asserting line clock
(pixel clock does not transition).
BLW - Beginning-of-line pixel clock wait count:
1 to 256 "dummy" pixel clock periods to wait after line clock negated before asserting pixel clocks
(pixel clock does not transition).
HSW - Horizontal sync pulse width:
0 to 64 "dummy" pixel clock periods to assert the line clock (pixel clock does not transition).
PPL - Pixels per line:
16 to 1024 pixels per line on the screen (must be programmed on 16 pixel multiples).
Frame clock asserted on first pixel clock of each frame, and is negated one "dummy" pixel clock
period before the first pixel clock of the 2nd line.
LEN set to 1
HSP = 0
VSP = 0
VSW = 1
PPL = 16
ELW = 2 HSW = 6
BLW = 2
Line 0 Data Line 1 Data Line 2 Data