Intel STRONGARM SA-1100 - Manual (Page 309)

SA-1100 Developer’s Manual 11-159
Peripheral Control Module
11.12.5.1 MCP Data Register 0
When MCP data register 0 (MCDR0) is read, the bottom entry of audio receive FIFO is accessed.
As data is removed by the MCP’s receive logic from the incoming data frame, it is placed into the
top entry of the audio receive FIFO and is transferred down an entry at a time until it reaches the
last empty location within the FIFO. Data is removed by reading MCDR, which accesses the
bottom entry of the audio FIFO. After MCDR0 is read, the bottom entry is invalidated and all
remaining values within the FIFO automatically transfer down one location.
When MCDR0 is written, the topmost entry of the audio transmit FIFO is accessed. After a write,
data is automatically transferred down to the lowest location within the transmit FIFO, which does
not already contain valid data. Data is removed from the bottom of the FIFO one value at a time by
the transmit logic, is loaded into the correct position within the 64-bit transmit serial shifter, and
then is serially shifted out onto the TXD4 pin during subframe 0.
Audio data is 12 bits wide and must be left justified by the user before writing it to the transmit FIFO
(MSB of audio data corresponds to bit 16 of transmit FIFO). The lower four bits of the FIFO are
automatically zero filled by the transmit logic when a 16-bit value is written to MCDR0 for
transmission. The UCB1100 or UCB1200 automatically forces bits 0 through 3 to zero before
transmitting the value to the MCP. The user must right justify received audio data before using it.
The following table shows MCDR0. Note that the transmit and receive audio FIFOs are cleared
when the SA-1100 is reset or by writing a zero to MCE (MCP disabled). Also note that writes to
reserved bits are ignored and reads return zeros.
Address: 0h 8006 0008 MCP Data Register 0: MCDR0 Read/Write
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bottom of Audio Receive FIFO 0 0 0 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Read Access
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Top of Audio Transmit FIFO 0 0 0 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Write Access
Bit Name Description
3..0 — Reserved for future enhancements.
Read – Data returned, but UCB1100 and UCB1200 currently zero fill these four bits.
Write – MCP’s transmit logic automatically zero fills these bits.
15..4 Audio
Data Transmit/receive audio FIFO data.
Read – Bottom of audio receive FIFO data.
Write – Top of audio transmit FIFO data.
31..16 — Reserved.