Intel STRONGARM SA-1100 - Manual (Page 374)

A-4 SA-1100 Developer’s Manual
Register Summary
LCD Controller Registers
0hB010 0000 LCCR0 LCD controller control register 0.
0hB010 0004 LCSR LCD controller status register.
0hB010 0008 – 0hB010 000C — Reserved.
0hB010 0010 DBAR1 DMA channel 1 base address register.
0hB010 0014 DCAR1 DMA channel 1 current address register.
0hB010 0018 DBAR2 DMA channel 2 base address register.
0hB010 001C DCAR2 DMA channel 2 current address register.
0hB010 0020 LCCR1 LCD controller control register 1.
0hB010 0024 LCCR2 LCD controller control register 2.
0hB010 0028 LCCR3 LCD controller control register 3.
0hB010 002C – 0hB010 FFFF — Reserved.
UDC Registers (Serial Port 0)
0h8000 0000 UDCCR UDC control register.
0h8000 0004 UDCAR UDC address register.
0h8000 0008 UCDOMP UDC OUT max packet register.
0h8000 000C UDCIMP UDC IN max packet register.
0h8000 0010 UDCCS0 UDC endpoint 0 control/status register.
0h8000 0014 UDCCS1 UDC endpoint 1 (out) control/status register.
0h8000 0018 UDCCS2 UDC endpoint 2 (in) control/status register.
0h8000 001C UDCD0 UDC endpoint 0 data register.
0h8000 0020 UDCWC UDC endpoint 0 write count register.
0h8000 0024 — Reserved.
0h8000 0028 UDCDR UDC transmit/receive data register (FIFOs).
0h8000 002C — Reserved.
0h8000 0030 UDCSR UDC status/interrupt register.
UART Registers (Serial Port 1)
0h 8001 0000 UTCR0 UART control register 0.
0h 8001 0004 UTCR1 UART control register 1.
0h 8001 0008 UTCR2 UART control register 2.
0h 8001 000C UTCR3 UART control register 3.
0h 8001 0010 — Reserved.
0h 8001 0014 UTDR UART data register.
0h 8001 0018 — Reserved.
0h 8001 001C UTSR0 UART status register 0.
0h 8001 0020 UTSR1 UART status register 1.
0h 8001 0024 – 0h 8001 FFFF — Reserved.
Physical Address Symbol Register Name