Intel STRONGARM SA-1100 - Manual (Page 149)

SA-1100 Developer’s Manual 10-35
Memory and PCMCIA Control Module
The following flow should be followed when coming out of reset, whether for sleep or power-up:
• Read boot ROM and write to memory configuration registers, but do not enable DRAM banks.
• If necessary, finish any DRAM power-up wait period (usually about 100 µs).
• If coming out of sleep, see Section 9.5, “Power Manager” on page 9-26 on how to release the
nCAS and nRAS pins from their self-refresh state.
• If coming out of sleep, wait the DRAM-specific post-self-refresh precharge period before
issuing a new DRAM transaction.
• If power-on reset, perform the number of initialization refreshes required by the specific
DRAM part by reading disabled banks. A read from any disabled bank will refresh all four
banks.
• Enable DRAM banks by setting MDCNFG:DE3:0.
10.8 Alternate Memory Bus Master Mode
The SA-1100 supports the existence of an alternate master on the memory bus. The alternate
master is given control of the memory bus (address, data, RAS, CAS, and static controls) using a
hardware handshake. This handshake is performed through MBREQ and MBGNT, which are
invoked through the alternate functions on GPIO<22> and GPIO<21> respectively. When the
alternate master wants to take control of the memory bus, it asserts MBREQ (GPIO<22>). The
SA-1100 will then complete any pending or in-progress memory operation and any outstanding
DRAM refresh cycle and then assert MBGNT (GPIO<21>). When the alternate master asserts
MBGNT, the SA-1100 will tristate the memory bus pins (A<25:0>, D<31:0>, nCS<3:0>, nOE,
NWE, nRAS<3:0>, nCAS<3:0> ).
During the tristate period, both MBREQ and MBGNT remain high and an external device may take
control of the tristated pins. It is recommended that the external device drive all the pins even if
some are not actually used. This will prevent floating inputs and the crossover current associated
with them. Note that during the tristate period, the SA-1100 is unable to perform DRAM refresh
cycles. The alternate master must assume the responsibility for DRAM integrity during this period.
It is recommended that the system be designed such that the period of alternate mastership is
limited to much less than the refresh period, or that the alternate master implement a refresh
counter making it capable of performing refresh at the proper intervals.
To give up the bus, the alternate master negates MBREQ. The SA-1100 will then negate MBGNT
and begin driving the bus. If the refresh counter inside the SA-1100 requested a refresh cycle
during the alternate master tenure, then that refresh cycle is run first, followed by any other bus
transactions that stalled during that period. This mode is set up by writing to the following
registers:
• GPIO pin direction register to program GIO<21> as an output and GPIO<22> as an input.
• GPIO alternate function register to program GPIO<21> and GPIO<22> to their alternate
function.
• Test unit control register (TUCR) to set bit 10.