Intel STRONGARM SA-1100 - Manual (Page 130)

10-16 SA-1100 Developer’s Manual
Memory and PCMCIA Control Module
Figure 10-3 shows the rate of the shift registers during DRAM nCAS timing for a single-beat
transaction.
Figure 10-3. DRAM Single-Beat Transactions
A4777-01
CPU Clock
Memory Clock
ADDR
Reads:
Latch Input Data
nOE
TRP
nRAS
nCAS
COL
DO
ROW ROW
Writes:
Input Data
DO Write Data
Contents of DRAM register fields:
MDCAS1 = 11 0001 1000 11000 (binary) MDCAS0 = 0110 0011 0001 1000 1100 0110 0000 0111 (binary)
nWE
first last
time
MDCNFG:TRP = 4 MDCNFG:CDB2 = 1 TDL = 00