3 register 2 – translation table base, 4 register 3 – domain access control, 5 register 4 – reserved – Intel STRONGARM SA-1100 User Manual
Page 48: 6 register 5 – fault status, 7 register 6 – fault address, Register 2 – translation table base -4, Register 3 – domain access control -4, Register 4 – reserved -4, Register 5 – fault status -4, Register 6 – fault address -4
5-4
SA-1100
Developer’s Manual
Coprocessors
5.2.3
Register 2 – Translation Table Base
Register 2 is a read/write register that holds the base of the currently active level 1 page table. Bits
<13:0> are undefined on read, ignored on write.
5.2.4
Register 3 – Domain Access Control
Register 3 is a read/write register that holds the current access control for domains 0 to 15. Refer to
the ARM Architecture Reference for a description of the domain structure
5.2.5
Register 4 – RESERVED
Register 4 is reserved. Accessing this register yields unpredictable results.
5.2.6
Register 5 – Fault Status
Reading register 5 returns the current contents of the fault status register (FSR). The FSR is written
when a data memory fault occurs or can be written by an MCR to the FSR. It is not updated for a
prefetch fault. See
Chapter 7, “Memory-Management Unit (MMU)”
for more details. Bits
<31:10> are undefined on read, ignored on write. Bit 9 is set when a data breakpoint is taken and
can be cleared by an MCR operation. Bit 8 is ignored on write and is always returned as zero.
Refer to the ARM Architecture Reference for a description of the domain and status fields.
5.2.7
Register 6 – Fault Address
Reading register 6 returns the current contents of the fault address register (FAR). The FAR is
written when a data memory fault occurs with the virtual address of the data fault or can be written
by an MCR to the FAR.
0
13
14
31
Translation Table Base
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
Domain
Status
0
3
4
7
8
9
31
D
10
0
31
Fault Virtual Address