Intel STRONGARM SA-1100 - Manual (Page 218)

11-68 SA-1100 Developer’s Manual
Peripheral Control Module
11.8.7 UDC Endpoint 0 Control/Status Register
The UDC endpoint zero control/status register contains 8 bits that are used to operate endpoint zero
(control endpoint).
11.8.7.1 OUT Packet Ready (OPR)
The OUT packet ready bit is set by the UDC when it receives a valid token to endpoint zero. When
this bit is set, the EIR bit will be set in the UDC status/interrupt register if endpoint zero interrupts
are enabled. This bit is cleared by writing a one to the serviced out packet ready bit (6). The UDC
is not allowed to enter the data phase of a transaction until this bit is cleared. If there is no data
phase, then the CPU should set the data end bit (4) at the same time it clears this bit.
11.8.7.2 IN Packet Ready (IPR)
The IN packet ready bit is set by the CPU after it has written a packet to the endpoint zero FIFO to
be transmitted. The UDC will automatically clear this bit when the packet has been successfully
transmitted. When this bit is cleared, the EIR bit in the UDC status/interrupt register will be set if
endpoint zero interrupts are enabled. The CPU will not be able to clear this bit.
11.8.7.3 Sent Stall (SST)
The sent stall bit is set by the UDC when it must abort the current control transfer by issuing a
STALL handshake due to a protocol violation. When this bit is set, the EIR bit in the UDC
status/interrupt register will be set if endpoint zero interrupts are enabled. The CPU clears this bit
by writing a one to it.
11.8.7.4 Force Stall (FST)
The force stall bit can be set by the UDC to force the UDC to issue a STALL handshake. The UDC
issues a STALL handshake for the current setup control transfer and the bit is cleared by the UDC
because endpoint zero cannot remain in a stalled condition.
11.8.7.5 Data End (DE)
The data end bit is set by the UDC after it writes the last packet for the current descriptor. Once the
current setup transfer has ended, the UDC clears this bit. When this bit is cleared the EIR bit in the
UDC status/interrupt register will be set if endpoint zero interrupts are enabled. If there is no data
phase, the CPU should set this bit at the same time it clears the OPR bit (0).
11.8.7.6 Setup End (SE)
The setup end bit is set by the UDC when a control transfer ends before the DE bit (4) gets set.
When this bit is set the EIR bit in the UDC status/interrupt register will be set if endpoint zero
interrupts are enabled. This bit is cleared by writing a one to the serviced setup end bit (7). When
the CPU detects this bit being set (if the OPR bit (0) is also set), then it should unload the new setup
packet after it clears setup end.
11.8.7.7 Serviced OPR (SO)
The serviced bit will clear the OPR bit (0) when writing a one.