Intel STRONGARM SA-1100 - Manual (Page 263)

SA-1100 Developer’s Manual 11-113
Peripheral Control Module
11.10.6.3 Transmit FIFO Underrun Select (TUS)
The transmit FIFO underrun select (TUS) bit is used both to select what action to take as a result of
a transmit FIFO underrun as well as mask or enable the transmit FIFO underrun interrupt.
When TUS=0, transmit FIFO underruns are used to signal the transmit logic that the end of the
frame has been reached. When the transmit FIFO experiences an underrun, the CRC value, which
is calculated continuously on outgoing data, is loaded to the serial shifter and transmitted, followed
by the stop flag and SIP pulse. Also when TUS=0, the transmit FIFO interrupt is masked and the
state of the transmit FIFO underrun (TUR) status bit is ignored by the interrupt controller.
When TUS=1, transmit FIFO underruns are used to signal the transmit logic that the end of the
frame has not yet been reached. When the transmit FIFO experiences an underrun, the CRC value,
which is calculated continuously on outgoing data, is loaded to the serial shifter and transmitted,
followed by the stop flag and SIP pulse. Additionally, when TUS=0, the transmit FIFO underrun
interrupt is masked, causing the state of the transmit FIFO underrun (TUR) status bit to be ignored
by the interrupt controller. Note that programming TUS=0 does not affect the current state of TUR
or the transmit FIFO logic’s ability to set and clear TUR; it only blocks the generation of the
interrupt request.
When TUS=1, transmit FIFO underruns are used to signal the transmit logic that the end of the
frame has not yet been reached and that the rate in which data is supplied to the transmit FIFO is
not sufficient. When the transmit FIFO experiences an underrun, two sequential chips, each
containing zeros (0000), are output by the transmitter to signal an abort condition; next a SIP pulse
is output, followed by a minimum of 16 preambles. Preambles continue to be output until data is
once again available within the transmit FIFO. Additionally, when TUS=1, the transmit FIFO
underrun interrupt is enabled, and whenever TUR is set (one), an interrupt request is made to the
interrupt controller. To change the state of TUS during operation, the user should fill the transmit
FIFO to ensure TUS is not written at the same time that the transmit FIFO underruns.
TUS is useful for ensuring that frames are not prematurely ended due to an unexpected transmit
FIFO underrun. At the start of a frame, the user can configure TUS=1 such that any underrun
signals an abort to the off-chip receiver. Just before the end of the frame, the user can then
configure TUS=0, allowing the remaining data to be output by the transmit logic. The FIFO then
underruns, causing the CRC, stop flag, and SIP to be transmitted.
11.10.6.4 Transmit Enable (TXE)
The transmit enable (TXE) bit is used to enable and disable HSSP transmit operation. When
TXE=0, the transmit logic is disabled and its clocks are turned off to conserve power. When
TXE=1, the HSSP transmitter logic is enabled for IrDA transmission. It is required that the user
first program all other control bits before setting TXE. If the TXE bit is cleared to zero while the
HSSP is actively transmitting data, transmission is stopped immediately, all data within the
transmit FIFO and serial output shifter is cleared, and control of the TXD2 pin is given to the
peripheral pin control (PPC) unit. When the transmitter is turned on (TXE=0
→
1), a SIP pulse is
transmitted before transmission of data. A SIP pulse is used to prevent slower devices (115.2 Kbps)
from attempting to take control of infrared transmission. See the previous sections for further
timing details of the SIP pulse.
TXE and RXE are the only control bits within the HSSP that are initialized when a hardware reset
occurs. Clearing TXE to zero ensures the HSSP transmitter is disabled, giving control of the
transmit pin to the PPC unit that configures TXD1 as an input following a reset of the SA-1100.
Note that TXE is ignored when ITR=0 (enables UART operation). Also note that even though the
IrDA standard permits only half-duplex operation, the HSSP does not restrict the user from