Intel STRONGARM SA-1100 - Manual (Page 223)

SA-1100 Developer’s Manual 11-73
Peripheral Control Module
11.8.9.7 Bits 7..6 Reserved
Bits 7..6 are reserved for future use.
Address: 0h 8000 0018 UDCCS2 Read/Write
Bit 7 6 5 4 3 2 1 0
Res. FST SST TUR TPE TPC TFS
Reset 0 0 0 0 0 0 0 0
Bit Name Description
0 TFS Transmit FIFO service (read-only).
0 – Transmit FIFO has more than 8 bytes.
1 – Transmit FIFO has 8 bytes or less.
1 TPC Transmit packet complete (read/write 1 to clear).
0 – Error/status bits invalid.
1 – Transmit packet has been sent and error/status bits are valid.
2 TPE Transmit packet error (read-only).
0 – Transmit packet was received with no errors.
1 – Transmit packet has errors and the host did not issue ACK. Valid only when RPC is
set.
3 TUR Transmit FIFO underrun.
1 – Transmit FIFO experienced an underrun. Valid only when TPC is set.
4 SST Sent STALL (read/write 1 to clear).
1 – STALL handshake was sent. Valid only when TPC is set.
5 FST Force STALL (read/write).
1 – Issue STALL handshakes to IN tokens.
7..6 — Reserved.
Always reads zero.