Intel STRONGARM SA-1100 - Manual (Page 52)

5-8 SA-1100 Developer’s Manual
Coprocessors
5.2.13 Register 14 – Debug Support (Breakpoints)
The SA-1100 supports address and data breakpoints through register 14 of coprocessor 15. The
instruction formats follow. For a description of the breakpoint operation, see
Chapter 15, “Debug
Support” . The following table shows the OPC_2 and CRm field encodings used to access the
address and data breakpoints.
The DBCR register is a 3-bit register used to control the enabling and disabling of the data
breakpoints. Bits 0..2 are valid and positioned as shown below. Bits 3..31 are reserved. These bits
read as zeros and writes have no effect.
The IBCR is a write-only register used to load an address breakpoint address and to set an enable
bit for the function. If an address is loaded with bit 0 (E) set, then the address is enabled as a
breakpoint. If bit zero is cleared, then the breakpoint is disabled. Bit 1 is reserved and should be
written to zero.
Function OPC_2 CRm
Access data breakpoint address register (DBAR). 0b000 0b0000
Access data breakpoint value register (DBVR). 0b000 0b0001
Access data breakpoint mask register (DBMR). 0b000 0b0010
Load data breakpoint control register (DBCR).
-----------------------------------------------------------------
DBCR Bit Action
-----------------------------------------------------------------
lw 0 = Disable load watch
1 = Enable load watch
saw 0 = Disable store address watch
1 = Enable store address watch
sdw 0 = Disable store data watch
1 = Enable store data watch
0b000 0b0011
Write instruction breakpoint address and control register (IBCR).
Low-order address bit is the address break enable/disable bit.
Register not readable.
0b000 0b1000
lw
0 2 31
saw sdw
1
Reserved
E
0 2 31
r
1
Instruction Address Breakpoint Value