Intel STRONGARM SA-1100 - Manual (Page 294)

11-144 SA-1100 Developer’s Manual
Peripheral Control Module
The following table shows the bit locations corresponding to the flag bits within UART status
register 1. Note that these flags do not generate interrupts, all bits are read-only, writes are ignored,
and reads of reserved bits return zeros.
Address: 0h 8005 0020 UTSR1 Read-Only
Bit 7 6 5 4 3 2 1 0
Reserved ROR FRE PRE TNF RNE TBY
Reset 0 0 0 0 0 1 0 0
Bit Name Description
0 TBY Transmitter busy flag (read-only).
0 – Transmitter is idle or UART is disabled.
1 – Transmit logic is currently transmitting a frame (data within the serial shifter); no
interrupt generated.
1 RNE Receive FIFO not empty (read-only).
0 – Receive FIFO is empty.
1 – Receive FIFO is not empty (no interrupt generated).
2 TNF Transmit FIFO not full (read-only).
0 – Transmit FIFO is full.
1 – Transmit FIFO is not full (no interrupt generated).
3 PRE Parity error (read-only).
0 – No parity errors encountered in the receipt of the next data value in the FIFO (or
parity disabled).
1 – Parity error encountered in the receipt of the next data value in the FIFO (no interrupt
generated).
4 FRE Framing error (read-only).
0 – Stop bit for the next frame in the FIFO was a one.
1– Stop bit for the next frame in the FIFO was a zero (no interrupt generated).
5 ROR Receive FIFO overrun (read-only).
0 – Receive FIFO has not experienced an overrun.
1 – Receive logic attempted to place data into receive FIFO while it was full, the next
data value in the FIFO is the last piece of “good” data before the FIFO was overrun (no
interrupt generated).
7..6 — Reserved.