Intel STRONGARM SA-1100 - Manual (Page 385)

SA-1100 Developer’s Manual D-1
Internal Test
Internal Test D
The Test Unit contains a register that enables certain test modes. Some of these test modes are
reserved for manufacturing test and should not be invoked by an end user.
D.1 Test Unit Control Register (TUCR)
The Test Unit Control Register (TUCR) contains control bits that put the Intel
®
StrongARM
®
SA-1100 Microprocessor (SA-1100) in various test modes. It is recommended that the operating
system write protect these registers under normal conditions to prevent them from being
inadvertently written. The following figure shows the format of this register. At reset reserved bits
are zero. Writing reserved bits to one can lead to UNPREDICTABLE results.
A6071-02
R/W
R/W
TSEL2 TSEL1 TSEL0 Reserved
Bit
Reset
31 30 29 28 27 26 25
0 0 0 0 0 0 0 0 0 0 0 0 0
24 23 22 21
MR PMD
20 19
0 0 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Reserved Reserved
18 17 16
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit Name Description
0..5 Reserved —
6 Reserved —
7 Reserved —
8 Reserved —
9 PMD Power management disable.
When PMD is set, sleep mode is disabled and the SA-1100 ignores the
ForceSleep bit, as well as the BATT_FAULT and VDD_Fault pins. This bit is
cleared on hard reset.
10 MR Memory request mode. Controls two GPIO pins used for external arbitration and
for the memory bus.
0 – GP<21> and GP<22> are not used for an alternate function.
1 – GP<21> and GP<22> are reserved for use as MBGNT and MBREQ,
respectively.
11..19 Reserved —
20 Reserved —
21 Reserved —
22 Reserved —
23 Reserved —
24 Reserved —
25 Reserved —
26 Reserved —