Intel STRONGARM SA-1100 - Manual (Page 322)

11-172 SA-1100 Developer’s Manual
Peripheral Control Module
Figure 11-37 shows the National Microwire
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frame format for a single transmitted frame and when
back-to-back frames are transmitted. Microwire format is very similar to SPI format, except that
transmission is half- instead of full-duplex, using a master-slave message passing technique. Each
serial transmission begins with an 8-bit control word that is transmitted from the SSP to the
off-chip slave device. During this transmit, no incoming data is received by the SSP. After the
message has been sent, the off-chip slave decodes it and responds with the requested data after
waiting one serial clock after the last bit of the 8-bit control message has been sent. The returned
data is 4 to 16 bits in length, making the total frame length anywhere from 13 to 25 bits.
SCLK and the transmit data line (TXD4) is forced low, and SFRM is forced high whenever the SSP
is disabled or following a reset of the SA-1100. Once enabled, transmission is triggered by writing
a control byte to the transmit FIFO. The falling edge of SFRM causes the value contained within
the bottom entry of the transmit FIFO to be transferred to the transmit logic’s serial shift register
and the MSB of the 8-bit control frame to be shifted onto the TXD4 pin. SFRM remains low for the
duration of the frame’s transmission. The RXD4 pin remains tristated during this transmission. The
off-chip serial slave device latches each control bit into its serial shifter on the rising edge of each
SCLK. After the last bit is latched by the slave device, the control byte is decoded during a
one-clock waitstate, and the slave responds by transmitting data back to the SSP, driving each bit
onto the RXD4 line on the falling edge of SCLK. The SSP, in turn, latches each bit on the rising
edge of SCLK. At the end of the frame, for single transfers, the SFRM signal is pulled high one
SCLK period after the last bit has been latched in the receive serial shifter, which causes the data to
be transferred to the receive FIFO. Note that the off-chip slave device can tristate the receive line
either on the falling edge of SCLK after the LSB has been latched by the receive shifter or when
the SFRM pin goes high. Also note that the transmit pin retains the last value it transmits (the value
of bit <0>, when the frame completes and the SSP enters idle mode). If the SSP is disabled or a rest
occurs, the transmit pin is reset to zero.
For continuous transfers, data transmission begins and ends in the same manner as a single transfer;
however, the SFRM line is continuously asserted (held low) and transmission of data occurs
back-to-back (the control byte of the next frame follows directly after the LSB of the received data
from the previous frame). Each of the received data values is transferred from the receive shifter on
the falling edge SCLK after the LSB of the frame has been latched into the SSP.
Figure 11-37. National Microwire
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Frame Format
SCLK
... ...
SFRM
... ...
TXD4 Bit<7> ... Bit<0> ...
8-Bit Control 1 Clk
RXD4 ... Bit ... Bit<0>
4 to 16 Bits
Single Transfer
SCLK
... ... ...
SFRM
... ... ...
TXD4 Bit<0> ... Bit<7> ... Bit<0> ...
1 Clk 1 Clk
RXD4 Bit ... Bit<0> ... Bit ... Bi
Continuous Transfers