Intel STRONGARM SA-1100 - Manual (Page 11)

SA-1100 Developer’s Manual xi
11.9.9.5Receive Transition Detect Status (RTD)
(read/write, noninterruptible)................................................ 11-99
11.9.9.6End of Frame Flag (EOF)
(read-only, noninterruptible)................................................. 11-99
11.9.9.7CRC Error Status (CRE)
(read-only, noninterruptible)............................................... 11-100
11.9.9.8Receiver Overrun Status (ROR)
(read-only, noninterruptible)............................................... 11-100
11.9.10 UART Register Locations ............................................................... 11-102
11.9.11 SDLC Register Locations ............................................................... 11-103
11.10 Serial Port 2 – Infrared Communications Port (ICP).................................... 11-103
11.10.1 Low-Speed ICP Operation.............................................................. 11-104
11.10.1.1HP-SIR* Modulation......................................................... 11-104
11.10.1.2 UART Frame Format ...................................................... 11-104
11.10.2 High-Speed ICP Operation ............................................................. 11-105
11.10.2.14PPM Modulation ............................................................ 11-105
11.10.2.2HSSP Frame Format ....................................................... 11-106
11.10.2.3Address Field................................................................... 11-107
11.10.2.4Control Field .................................................................... 11-107
11.10.2.5Data Field ........................................................................ 11-107
11.10.2.6CRC Field ........................................................................ 11-107
11.10.2.7Baud Rate Generation ..................................................... 11-108
11.10.2.8Receive Operation ........................................................... 11-108
11.10.2.9Transmit Operation .......................................................... 11-109
11.10.2.10Transmit and Receive FIFOs......................................... 11-110
11.10.2.11CPU and DMA Register Access Sizes .......................... 11-110
11.10.3 UART Register Definition................................................................ 11-111
11.10.4 UART Control Register 4 ................................................................ 11-111
11.10.4.1HP-SIR Enable (HSE)...................................................... 11-111
11.10.4.2Low-Power Mode (LPM) .................................................. 11-111
11.10.5 HSSP Register Definitions.............................................................. 11-112
11.10.6 HSSP Control Register 0 ................................................................ 11-112
11.10.6.1IrDA Transmission Rate (ITR) ......................................... 11-112
11.10.6.2Loopback Mode (LBM) .................................................... 11-112
11.10.6.3Transmit FIFO Underrun Select (TUS) ............................ 11-113
11.10.6.4Transmit Enable (TXE) .................................................... 11-113
11.10.6.5Receive Enable (RXE)..................................................... 11-114
11.10.6.6Receive FIFO Interrupt Enable (RIE)............................... 11-114
11.10.6.7Transmit FIFO Interrupt Enable (TIE) .............................. 11-114
11.10.6.8Address Match Enable (AME) ......................................... 11-114
11.10.7 HSSP Control Register 1 ................................................................ 11-116
11.10.7.1Address Match Value (AMV) ........................................... 11-116
11.10.8 HSSP Control Register 2 ................................................................ 11-117
11.10.8.1Transmit Pin Polarity Select (TXP) .................................. 11-117
11.10.8.2Receive Pin Polarity Select (RXP)................................... 11-117
11.10.9 HSSP Data Register ....................................................................... 11-119
11.10.10HSSP Status Register 0 ................................................................ 11-121
11.10.10.1End/Error in FIFO Status (EIF)
(read-only, nonmaskable interrupt).................................... 11-121
11.10.10.2Transmit Underrun Status (TUR)
(read/write, maskable interrupt) ......................................... 11-121
11.10.10.3Receiver Abort Status (RAB)
(read/write, nonmaskable interrupt) ................................... 11-121