Intel STRONGARM SA-1100 - Manual (Page 246)

11-96 SA-1100 Developer’s Manual
Peripheral Control Module
11.9.8 SDLC Status Register 0
SDLC status register 0 (SDSR0) contains bits that signal the transmit FIFO service request, receive
FIFO service request, receiver abort, transmit FIFO underrun, and the end/error in receive FIFO
condition. Each of these hardware-detected events signal an interrupt request to the interrupt controller.
A bit that can cause an interrupt signals the interrupt request as long as the bit is set. Once the bit is
cleared, the interrupt is cleared. Read/write bits are called status bits; read-only bits are called flags.
Status bits are referred to as “sticky” (once set by hardware, must be cleared by software). Writing
a one to a sticky status bit clears it; writing a zero has no effect. Read-only flags are set and cleared
by hardware; writes have no effect. Additionally, some bits that cause interrupts have
corresponding enable/mask bits in the control registers and are indicated in the following section
headings. Note that the user has the ability to mask all SDLC interrupts by clearing bit 14 within
the interrupt controller mask register (ICMR). See the
Section 9.2, “Interrupt Controller” on
page 9-11 .
11.9.8.1 End/Error in FIFO Status (EIF) (read-only, nonmaskable interrupt)
The end/error in FIFO flag (EIF) is a read-only bit that is set when any tag bits (8 through 10) are set
within the bottom four entries of the receive FIFO and is cleared when no error bits are set within the
bottom four entries of the FIFO. When EIF is set, an interrupt is signalled and DMA requests to
empty the receive FIFO are disabled until EIF is cleared. To discover which FIFO entry contains the
end of frame or an error condition, the user should check the state of the EOF, CRE, and ROR bits and
read the corresponding value from the SDDR. This procedure should be repeated until EIF is cleared
because set tag bits that are present within any of the four lowest entries in the receive FIFO can set
EIF. Once all set tags bits are cleared from the bottom half of the receive FIFO, EIF is automatically
cleared, which in turn, clears the interrupt and reenables the receive FIFO DMA request.
11.9.8.2 Transmit Underrun Status (TUR) (read/write, maskable interrupt)
The transmit underrun status bit (TUR) is set when the transmit logic attempts to fetch data from the
transmit FIFO after it has been completely emptied. When an underrun occurs, the transmitter takes
one of two actions. When the transmit underrun select bit is clear (TUS=0), the transmitter ends the
frame by shifting out the CRC that is calculated continuously on outgoing data, followed by a flag.
When TUS=1, the transmitter is forced to transmit an abort and continues to transmit ones until valid
data is again available within the FIFO. Once data resides within the bottom entry of the transmit
FIFO, a new data frame is initiated by transmitting a start flag followed by the transmission of data
from the FIFO. When the TUR bit is set, an interrupt request is made unless it is masked. When
TUS=0, the interrupt is masked; when TUS=1 it is enabled. Note that underruns are not generated
when the SDLC transmitter is first enabled and is in the idle state (continuously transmits flags).
11.9.8.3 Receiver Abort Status (RAB) (read/write, maskable interrupt)
The receiver abort status bit (RAB) is set for three different cases:
• when an abort is detected during receipt of an incoming frame
• if the receive carrier is lost during active operation
• if the stop flag is not received on a byte boundary.
An abort is signalled when seven or more consecutive ones are detected on the RXD1 pin. An abort
is also signalled if the receive pin is held high or low for more than six bit periods, which indicates
a loss of carrier. It is also generated when the end flag is received and it is not on a byte boundary,