Intel STRONGARM SA-1100 - Manual (Page 87)

SA-1100 Developer’s Manual 9-17
System Control Module
9.2.2 Interrupt Controller Register Locations
The following table shows the registers associated with the interrupt controller block and the
physical addresses used to access them.
9.3 Real-Time Clock
The SA-1100 contains a real-time clock (RTC) that provides a general-purpose real-time reference
for use by the system. The RTC is uninitialized after a hardware reset (nRESET) and must be
written by the user to the desired value. Thereafter, the counter will remain valid until another
hardware reset (assumed to be infrequent). The value of the counter is unaffected by transitions
into and out of sleep, idle, software reset, or a watchdog reset. The counter is incremented on rising
edges of the 1-Hz clock.
In addition to the counter [ RTC counter register (RCNR) ], the RTC incorporates a 32-bit alarm
register (RTAR). The RTAR may be programmed with a value to be compared against the counter.
On each rising edge of the 1-Hz clock, the counter is incremented and then compared to the RTAR.
If the values match, then a status bit is set. This status bit is also routed to the interrupt controller
and may be programmed to generate a CPU interrupt.
Another interruptible status bit is available that is set whenever the 1 Hz clock ticks. Each status bit
may be cleared by writing a one to the status register in the desired bit position. The 1-Hz clock is
generated by dividing down the 32.768-kHz crystal oscillator output. This divider logic is
programmable to allow the user to “trim” the counter to adjust for inherent inaccuracies in the
crystal’s frequency. This trimming mechanism permits the user to adjust the RTC to an accuracy of
+/- 5 seconds per month. The trimming procedure is described later in this section.
9.3.1 RTC Counter Register (RCNR)
The RTC counter register (RCNR) is a read/write register and is not cleared by any reset source.
The counter may be written by the processor at any time although it is recommended that the
operating system prevent inadvertent writes to the RCNR through the use of the MMU protection
mechanisms.
Because of the asynchronous nature of the 1-Hz clock relative to the processor clock, writes to this
counter are controlled by a hardware mechanism that delays the actual write to the counter by up to
one 32-kHz-clock (~ 30 µs) after the processor store is performed.
After the processor writes to the RCNR, all other writes to this register location are ignored until
the new value is actually loaded into the counter. The RCNR may be read at any time. Reads reflect
the value in the counter immediately after it increments or loads.
Address Name Description
0h 9005 0000 ICIP Interrupt controller IRQ pending register
0h 9005 0004 ICMR Interrupt controller mask register
0h 9005 0008 ICLR Interrupt controller level register
0h 9005 0010 ICFP Interrupt controller FIQ pending register
0h 9005 0020 ICPR Interrupt controller pending register
0h 9005 000C ICCR Interrupt controller control register