Intel STRONGARM SA-1100 User Manual
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SA-1100 Developer’s Manual
11.9.1.5Data Field ............................................................................ 11-81
11.9.1.6CRC Field ............................................................................ 11-81
11.9.1.7Baud Rate Generation ......................................................... 11-81
11.9.1.8Receive Operation ............................................................... 11-82
11.9.1.9Transmit Operation .............................................................. 11-83
11.9.1.10Simultaneous Use of the UART and SDLC ....................... 11-83
11.9.1.11Transmit and Receive FIFOs............................................. 11-84
11.9.1.12CPU and DMA Register Access Sizes .............................. 11-84
11.9.2 SDLC Register Definitions ................................................................ 11-84
11.9.3 SDLC Control Register 0 .................................................................. 11-85
11.9.3.1SDLC/UART Select (SUS)................................................... 11-85
11.9.3.2Single/Double Flag Select (SDF)......................................... 11-85
11.9.3.3Loopback Mode (LBM) ........................................................ 11-85
11.9.3.4Bit Modulation Select (BMS)................................................ 11-86
11.9.3.5Sample Clock Enable (SCE) ............................................... 11-86
11.9.3.6Sample Clock Direction (SCD) ............................................ 11-86
11.9.3.7Receive Clock Edge Select (RCE) ...................................... 11-87
11.9.3.8Transmit Clock Edge Select (TCE)...................................... 11-87
11.9.4.1Abort After Frame (AAF)...................................................... 11-88
11.9.4.2Transmit Enable (TXE) ........................................................ 11-89
11.9.4.3Receive Enable (RXE)......................................................... 11-89
11.9.4.4Receive FIFO Interrupt Enable (RIE)................................... 11-89
11.9.4.5Transmit FIFO Interrupt Enable (TIE) .................................. 11-89
11.9.4.6Address Match Enable (AME) ............................................. 11-90
11.9.4.7Transmit FIFO Underrun Select (TUS) ................................ 11-90
11.9.4.8Receiver Abort Interrupt Enable(RAE)................................. 11-90
11.9.5.1Address Match Value (AMV) ............................................... 11-92
11.9.6 SDLC Control Registers 3 and 4 ...................................................... 11-93
11.9.6.1Baud Rate Divisor (BRD)..................................................... 11-93
11.9.7 SDLC Data Register ......................................................................... 11-94
11.9.8 SDLC Status Register 0 ................................................................... 11-96
11.9.8.1End/Error in FIFO Status (EIF)
(read-only, nonmaskable interrupt)...................................... 11-96
11.9.8.2Transmit Underrun Status (TUR)
(read/write, maskable interrupt) ........................................... 11-96
11.9.8.3Receiver Abort Status (RAB)
(read/write, maskable interrupt) ........................................... 11-96
11.9.8.4Transmit FIFO Service Request Flag (TFS)
(read-only, maskable interrupt)............................................ 11-97
11.9.8.5Receive FIFO Service Request Flag (RFS)
(read-only, maskable interrupt)............................................ 11-97
11.9.9.1Receiver Synchronized Flag (RSY)
(read-only, noninterruptible)................................................. 11-99
11.9.9.2Transmitter Busy Flag (TBY)
(read-only, noninterruptible)................................................. 11-99
11.9.9.3Receive FIFO Not Empty Flag (RNE)
(read-only, noninterruptible)................................................. 11-99
11.9.9.4Transmit FIFO Not Full Flag (TNF)
(read-only, noninterruptible)................................................. 11-99