Intel STRONGARM SA-1100 - Manual (Page 221)

SA-1100 Developer’s Manual 11-71
Peripheral Control Module
11.8.8.7 Bits 7..6 Reserved
Bits 7..6 are reserved for future use.
Address: 0h 8000 0014 UDCCS1 Read/Write
Bit 7 6 5 4 3 2 1 0
Res. RNE FST SST RPE RPC RFS
Reset 0 0 0 0 0 0 0 0
Bit Name Description
0 RFS
Receive FIFO service (read-only).
0 – Receive FIFO has less than 12 bytes.
1 – Receive FIFO has 12 bytes or more.
1 RPC
Receive packet complete (read/write 1 to clear).
0 – Error/status bits invalid.
1 – Receive packet has been received and error/status bits are valid.
2 RPE
Receive packet error (read-only).
0 – Receive packet has no errors.
1 – Receive packet has errors; valid only when RPC is set.
3 SST
Sent stall (read/write 1 to clear).
1 – STALL handshake was sent; valid only when RPC is set.
4 FST
Force stall (read/write).
1 – Issue STALL handshakes to OUT tokens.
5 RNE
Receive FIFO not empty (read-only).
0 – Receive FIFO empty.
1 – Receive FIFO not empty.
7..6 —
Reserved.
Always reads zero.