Intel STRONGARM SA-1100 - Manual (Page 13)

SA-1100 Developer’s Manual xiii
11.11.7.2Receive FIFO Service Request Flag (RFS)
(read-only, maskable interrupt).......................................... 11-139
11.11.7.3Receiver Idle Status (RID)
(read/write, maskable interrupt) ......................................... 11-140
11.11.7.4Receiver Begin of Break Status (RBB)
(read/write, nonmaskable interrupt) ................................... 11-140
11.11.7.5Receiver End of Break Status (REB)
(read/write, nonmaskable interrupt)11-140
11.11.7.6Error in FIFO Flag (EIF)
(read-only, nonmaskable interrupt).................................... 11-140
11.11.8 UART Status Register 1 ................................................................. 11-142
11.11.8.1Transmitter Busy Flag (TBY
(read-only, noninterruptible)............................................... 11-142
11.11.8.2Receive FIFO Not Empty Flag (RNE)
(read-only, noninterruptible)............................................... 11-142
11.11.8.3Transmit FIFO Not Full Flag (TNF)
(read-only, noninterruptible)............................................... 11-142
11.11.8.4Parity Error Flag (PRE)
(read-only, noninterruptible)............................................... 11-142
11.11.8.5Framing Error Flag (FRE)
(read-only, noninterruptible)............................................... 11-143
11.11.8.6Receiver Overrun Flag (ROR)
(read-only, noninterruptible)............................................... 11-143
11.11.9 UART Register Locations ............................................................... 11-145
11.12 Serial Port 4 – MCP / SSP........................................................................... 11-145
11.12.1 MCP Operation ............................................................................... 11-146
11.12.1.1Frame Format .................................................................. 11-147
11.12.1.2Audio and Telecom Sample Rates and Data Transfer .... 11-148
11.12.1.3MCP Transmit and Receive FIFO Operation ................... 11-149
11.12.1.4Codec Control Register Data Transfer ............................ 11-150
11.12.1.5External Clock Operation ................................................. 11-151
11.12.1.6Alternate SSP Pin Assignment ........................................ 11-151
11.12.1.7CPU and DMA Register Access Sizes ............................ 11-151
11.12.2 MCP Register Definitions................................................................ 11-152
11.12.3 MCP Control Register..................................................................... 11-152
11.12.3.1Audio Sample Rate Divisor (ASD) ................................... 11-152
11.12.3.2Telecom Sample Rate Divisor (TSD)............................... 11-153
11.12.3.3 Multimedia Communications Port Enable (MCE) .......... 11-154
11.12.3.4External Clock Select (ECS) ............................................ 11-154
11.12.3.5A/D Sampling Mode (ADM) ............................................. 11-154
11.12.3.6Telecom Transmit FIFO Interrupt Enable (TTE) .............. 11-155
11.12.3.7Telecom Receive FIFO Interrupt Enable (TRE)............... 11-155
11.12.3.8Audio Transmit FIFO Interrupt Enable (ATE) .................. 11-155
11.12.3.9Audio Receive FIFO Interrupt Enable (ARE) ................... 11-155
11.12.3.10Loopback Mode (LBM) .................................................. 11-156
11.12.3.11External Clock Prescaler (ECP)..................................... 11-156
11.12.4 MCP Control Register 1.................................................................. 11-158
11.12.4.1Clock Frequency Select (CFS) ........................................ 11-158
11.12.5 MCP Data Registers ....................................................................... 11-158
11.12.5.1MCP Data Register 0 ....................................................... 11-159
11.12.5.2MCP Data Register 1 ....................................................... 11-160
11.12.5.3MCP Data Register 2 ....................................................... 11-161
11.12.6 MCP Status Register ...................................................................... 11-163