Intel STRONGARM SA-1100 - Manual (Page 239)

SA-1100 Developer’s Manual 11-89
Peripheral Control Module
11.9.4.2 Transmit Enable (TXE)
The transmit enable (TXE) bit is used to enable and disable SDLC transmit operation. When
TXE=0, the transmit logic is disabled and its clocks are turned off to conserve power. When
TXE=1, the SDLC transmitter logic is enabled for serial transmission. It is required that the user
first program all other control bits before setting TXE. If the TXE bit is cleared to zero while the
SDLC is actively transmitting data, transmission is stopped immediately, all data within the
transmit FIFO and serial output shifter is cleared, and control of the TXD1 pin is given to the
peripheral pin control (PPC) unit. Note that SUS, TXE, and RXE are the only control bits within
the SDLC that are initialized when a hardware reset occurs. Clearing TXE to zero ensures the
SDLC transmitter is disabled, giving control of the transmit pin to the PPC unit, which configures
TXD1 as an input following a reset of the SA-1100. Note that TXE is ignored when SUS=1
(enables UART operation).
11.9.4.3 Receive Enable (RXE)
The receive enable (RXE) bit is used to enable or disable SDLC receive operation. When RXE=0,
the receive logic is disabled and its clocks are turned off to conserve power. When RXE=1, the
SDLC receiver logic is enabled for serial reception. It is required that the user first program all
other control bits before setting RXE. If the RXE bit is cleared to zero while the SDLC is actively
receiving data, reception is stopped immediately, all data within the receive FIFO and serial input
shifter is cleared, and control of the RXD1 pin is given to the peripheral pin control (PPC) unit.
Note that SUS, TXE, and RXE are the only control bits within the SDLC that are initialized when a
hardware reset occurs. Clearing RXE to zero ensures the SDLC receiver is disabled, giving control
of the receive pin to the PPC unit, which configures RXD1 as an input following a reset of the
SA-1100. Note that RXE is ignored when SUS=1 (enables UART operation).
11.9.4.4 Receive FIFO Interrupt Enable (RIE)
The receive FIFO interrupt enable (RIE) bit is used to mask or enable the receive FIFO service
request interrupt. When RIE=0, the interrupt is masked and the state of the receive FIFO service
request (RFS) bit within SDLC status register 0 is ignored by the interrupt controller. When RIE=1,
the interrupt is enabled and whenever RFS is set (one), an interrupt request is made to the interrupt
controller. Note that programming RIE=0 does not affect the current state of RFS or the receive
FIFO logic’s ability to set and clear RFS; it only blocks the generation of the interrupt request. Also
note that RIE does not affect generation of the receive FIFO DMA request, which is asserted
whenever RFS=1.
11.9.4.5 Transmit FIFO Interrupt Enable (TIE)
The transmit FIFO interrupt enable (TIE) bit is used to mask or enable the transmit FIFO service
request interrupt. When TIE=0, the interrupt is masked and the state of the transmit FIFO service
request (TFS) bit within SDLC status register 0 is ignored by the interrupt controller. When TIE=1,
the interrupt is enabled, and whenever TFS is set (one), an interrupt request is made to the interrupt
controller. Note that programming TIE=0 does not affect the current state of TFS or the transmit
FIFO logic’s ability to set and clear TFS; it only blocks the generation of the interrupt request. Also
note that TIE does not affect generation of the transmit FIFO DMA request, which is asserted
whenever TFS=1.