Intel STRONGARM SA-1100 - Manual (Page 110)

9-40 SA-1100 Developer’s Manual
System Control Module
9.5.7.8 Power Manager Oscillator Status Register (POSR)
The power manager oscillator status register (POSR) is a single-bit, read-only register that contains
a status bit indicating whether the 32.768-kHz oscillator is up to speed after a hardware reset. This
bit is set after the expiration of a timer that is clocked by a ring oscillator. This bit will be set within
2–10 seconds after the negation of nRESET.
9.5.8 Power Manager Register Locations
Table 9-4 shows the registers associated with the power manager and the physical addresses used
to access them
.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R/W Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R/W Reserved OOK
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit Name Description
0 OOK Oscillator OK.
This bit is cleared on a hardware reset and set after the 32.768-kHz oscillator has
stabilized. This bit is read only.
31..28 — Reserved.
Table 9-4. Power Manager Register Locations
Address Name Description
0h 9002 0000 PMCR Power manager control register
0h 9002 0004 PSSR Power manager sleep status register
0h 9002 0008 PSPR Power manager scratch pad register
0h 9002 000C PWER Power manager wake-up enable register
0h 9002 0010 PCFR Power manager general configuration register
0h 9002 0014 PPCR Power manager PLL configuration register
0h 9002 0018 PGSR Power manager GPIO sleep state register
0h 9002 001C POSR Power manager oscillator status register