Intel STRONGARM SA-1100 - Manual (Page 135)

SA-1100 Developer’s Manual 10-21
Memory and PCMCIA Control Module
Figure 10-7. Eight Beat Burst Read from Burst-of-Four ROM
Figure 10-8. Nonburst ROM, SRAM, or Flash Read Timing Diagram – Four Data Beats
A4781-01
Memory Clock
nCS0
RDF+1.5 RDF+1
RDN+1 RDN+1 RDN+1 RDN+1 RDN+1 RDN+1
(2*RRR)+1
A[25:5]
A[4]
nOE
Input Data
Latch
nCS1
Input Data
A[3:2] 0
D0 D1 D2 D3 D4 D5 D6
1 2 3 0 1 2 3
A4782-01
Memory Clock
nCS0
RDF+1.5
RDF+1
nCAS[3:0]
nOE
(SRAM only)
Read
(Input) Data
nCS1
Latch
Read Data
A[25:0]
RDF+1 RDF+1
(2*RRR)+1
A0 A1 A2 A3
D0 D1 D2 D3