5 interrupt controller control register (iccr), 5 interrupt controller control register (iccr) -16, System control module – Intel STRONGARM SA-1100 User Manual
Page 86
9-16
SA-1100
Developer’s Manual
System Control Module
9.2.1.5
Interrupt Controller Control Register (ICCR)
The interrupt controller control register (ICCR) contains a single control bit, the disable idle mask
bit (DIM). When set, this bit inhibits the idle mode operation where the output of the ICMR is
OR’ed to all ones. If this bit is set, then the interrupts that are capable of bringing the SA-1100 out
of idle mode are defined by the contents of the ICMR. The following table shows the location of all
interrupt level bits in the ICCR.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R/W
Reserved
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R/W
Reserved
DIM
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
Name
Description
{0}
DIM
Disable idle mask.
0 – All enabled interrupts will bring the SA-1100 out of idle mode.
1 – Only enabled and unmasked (as defined in the ICMR) will bring the SA-1100 out of
idle mode. This bit is cleared during all resets.
1..31
—
Reserved.