Intel STRONGARM SA-1100 - Manual (Page 280)

11-130 SA-1100 Developer’s Manual
Peripheral Control Module
The parity, framing, and overrun error bits are transferred down the receive FIFO along with the data
that caused the error. Whenever any of the four bottom FIFO entries contain one or more error bits that
are set, an interrupt is generated and receive FIFO DMA requests are disabled until the error is flushed
from the FIFO and the status bit that signalled the interrupt is cleared. At this point, the user should use
programmed I/O to check the error bits and remove data one piece at a time until the four FIFO entries
are flushed. Each time a data value is transferred to the bottom of the FIFO, the state of the parity,
framing, and overrun bits within the last FIFO entry are automatically transferred to their respective
flag bits in the status register. When any of these three flags are set in the UART status register, it
indicates that the next data value available within the FIFO contains an error. The user must first check
the state of these three flags to see if the next value within the FIFO contains an error, then read the
FIFO value. After four values have been removed from the FIFO and the errors are identified, the
DMA is automatically reenabled once the error in FIFO bits are removed from the FIFO.
If the receive FIFO contains valid data and three frame periods elapse without the reception of data
on RXD3, the receiver idle interrupt is generated. Also, if the receive logic detects a null character
(all zeros, including the parity bit) followed by a framing error (stop bit is zero as well), the receive
logic generates a beginning of break detect, which interrupts the CPU. Because breaks can be
signalled for long periods of time, after the break is negated and the receive pin transitions high, the
receive logic generates an end of break detect, which again interrupts the CPU.
11.11.1.4 Transmit Operation
The UART transmit logic operates at the same time as the receive logic (full-duplex). Data is taken
from the transmit FIFO; start, parity, and stop bits are added to generate a frame; and the value is
loaded into a serial shift register. The contents are shifted out onto the TXD3 pin, clocked by the
programmed baud clock. When the transmit FIFO is emptied more than halfway, an interrupt or
DMA request is signalled. If the transmit FIFO is completely emptied, the transmit line remains
high (one) after the last data value is transmitted to indicate the transmitter is idle. The TXD3 pin
remains high until additional data is written to the transmit FIFO.
11.11.1.5 Transmit and Receive FIFOs
To reduce chip size and power consumption, the UART’s FIFOs use self-timed logic (they are not
clocked). Because of process and environmental variations, the depth at which a service request is
triggered to empty the receive FIFO is variable. This variation spans a maximum of four FIFO
entries; the receive FIFO service request can be made at four different FIFO depths.To compensate
for this variability and guarantee that at least four valid entries of data exist within the FIFO before
generating a service request, an extra four entries have been added to the receive FIFO (four entries
more than the transmit FIFO). The transmit FIFO is 8 entries deep and the receive FIFO is 12
entries deep. The point at which the receive FIFO service request is triggered spans the middle
third of the 12-entry FIFO. The service request is signalled at a depth from one-third full to
two-thirds full (when the FIFO contains five, six, seven, or eight entries of data).
This service request variation applies only to an empty FIFO that is filled (receive FIFO). It does
not apply to a full FIFO that is emptied (transmit FIFO). The transmit FIFO is guaranteed to signal
a service request when it has four or more empty entries and negate the request when the FIFO
contains five or more entries that are filled.
If the DMA is used to service either one or both of the UART’s FIFOs, the burst size must be set to
4 words even though more than four entries of data may exist within the receive FIFO. If
programmed I/O is used to service the FIFOs, a maximum of 4 words may be added to the transmit
FIFO without checking if more space is available. Likewise, a maximum of 4 words may be