Intel STRONGARM SA-1100 - Manual (Page 202)

11-52 SA-1100 Developer’s Manual
Peripheral Control Module
Figure 11-11. Passive Mode End-of-Frame Timing
A4791-01
L_FCLK
L_LCLK
L_PCLK
LDD[x:0]
Notes:
BLW - Beginning-of-line pixel clock wait count:
0 to 256 "dummy" pixel clock periods to wait after line clock is negated before asserting pixel
clocks (pixel clock does not transition).
VSW - Vertical sync pulse width:
In passive mode, 1 to 64 line clock periods to wait between the end of one frame and the
beginning of the next frame (line clock transitions).
ELW - End-of-line pixel clock wait count:
1 to 256 "dummy" pixel clock periods to wait after last pixel in line before asserting line clock
(pixel clock does not transition).
LPP - Lines per panel:
1 to 1024 lines per panel.
Line 479 Data Line 0 Data
LPP = 480
VSW = 2
BLW = 1
ELW = 1