Intel STRONGARM SA-1100 - Manual (Page 118)

10-4 SA-1100 Developer’s Manual
Memory and PCMCIA Control Module
10.1.2 Types of Memory Accesses
The SA-1100 performs memory accesses for the following operations:
SA-1100 will only generate a subset of all possible transactions on the bus. Many of these
transactions may be completed internal to the processor by accessing caches, the read buffer,
on-chip registers, or the memory space that returns zeroes for flushing the cache.
If a memory access is followed by an idle period on the bus, the control signals will return to their
inactive state and the address and data signals will remain at their previous values to avoid
unnecessary bus transitions and eliminating the need for many pull-up resistors.
10.1.3 Reads
Read bursts are generated by DMA requests, read buffer requests, and cache line fills. All cache
line fills are 8 words long. DMA and read buffer requests may be 1, 4, or 8 words long. All other
reads are single accesses.
Data and instruction cache line fills start on an 8-word boundary and will be 8 words long.
10.1.4 Writes
For single access writes, one byte, half-word, or word is written. The write burst sizes are 1, 2, 3, or
4 full words. A write burst size of 8 words may be generated by castouts and all 32 bytes are
written.
For stores to DRAM or SRAM memory spaces, the nCAS<3:0> lines enable a corresponding byte
of the data bus during a write transaction. Flash memory space stores must be the width of the
Flash data bus, either 16 or 32 bits.
10.1.5 Transaction Summary
Table 10-1 lists all the transactions that the SA-1100 can generate. No burst will cross an aligned
32-byte boundary. Note that on a 16-bit bus, the read single operation becomes a two half-word
burst with address bit 1 always starting at 0. Writes to Flash memory space will take place in one
single operation regardless of bus size.
Unbuffered write
Uncached read
Buffered write
Linefetch
Read buffer fetch
Internal DMA write
Level 1 translation fetch
Level 2 translation fetch
Cache line copyback
Read-lock-write sequence
Internal DMA read