Intel STRONGARM SA-1100 - Manual (Page 292)

11-142 SA-1100 Developer’s Manual
Peripheral Control Module
11.11.8 UART Status Register 1
UART status register 1 (UTSR1) contains flags that indicate when the UART is actively
transmitting characters, that the transmit FIFO is not full, that the receive FIFO is not empty, and
when parity, framing, overrun, and underrun errors have occurred. All bits within UTSR1 are
read-only and are noninterruptible.
11.11.8.1 Transmitter Busy Flag (TBY) (read-only, noninterruptible)
The transmitter busy (TBY) flag is a read-only bit that is set when the transmitter is actively
processing data for transmission (the serial shifter contains data), and is cleared when the
transmitter is idle or is disabled (TXE=0). This bit does not request an interrupt.
11.11.8.2 Receive FIFO Not Empty Flag (RNE) (read-only, noninterruptible)
The receive FIFO not empty flag (RNE) is a read-only bit that is set when the receive FIFO
contains one or more bytes of valid data and is cleared when it no longer contains any valid data.
This bit can be polled when using programmed I/O to remove remaining bytes of data from the
receive FIFO because DMA service and CPU interrupt requests are made only when 8, 7, 6, or 5
bytes reside within the FIFO. This bit does not request an interrupt.
11.11.8.3 Transmit FIFO Not Full Flag (TNF) (read-only, noninterruptible)
The transmit FIFO not full flag (TNF) is a read-only bit that is set when the transmit FIFO contains
one or more entries that do not contain valid data and is cleared when the FIFO is completely full.
This bit can be polled when using programmed I/O to fill the transmit FIFO over its halfway mark.
This bit does not request an interrupt.
11.11.8.4 Parity Error Flag (PRE) (read-only, noninterruptible)
The parity error flag (PRE) is set when parity is enabled (PE = 1), and the parity type programmed
using OES does not correspond to the parity check of the incoming serial data stream, which is
calculated by the receive logic. The parity error bit is set when PE=1, OES=0, and UTDR<7:0>,
and the incoming parity bit contain an even number of ones, or PE=1, OES=1, and UTDR<7:0>,
and the incoming parity bit contain an odd number of ones.
The receive FIFO contains three bits (8, 9, and 10) that are not directly readable. The 8th bit in the
FIFO is set at the top of the FIFO whenever a byte of data that incurs a parity error is moved from
the receive serial shifter to the top of the receive FIFO. This tag travels along with the errant data
value as it moves down the FIFO. Each time a data value is transferred to the bottom of the FIFO
(caused by a read of the previous value), the state of this bit is moved from the FIFO to the PRE bit
in the status register. After the error in FIFO (EIF) status bit is set, the user should always read
UTSR1 first to check PRE before reading the data value from UDR because PRE corresponds to
the current data byte at the bottom of the receive FIFO and is updated each time data is removed
from the FIFO.