Intel STRONGARM SA-1100 - Manual (Page 103)

SA-1100 Developer’s Manual 9-33
System Control Module
9.5.7 Power Manager Registers
The power manager is controlled through eight 32-bit registers. The power manager control
register (PMCR) is used to allow software invocation of sleep mode. The sleep status register
(PSSR) contains status bits that indicate why sleep mode was invoked. The power manager
scratchpad register (PSPR) is a general-purpose register used to store processor data during sleep.
The power manager wake-up enable register (PWER) is used to program the desired wake-up
sources in the system. The power manager general configuration register (PCFR) contains bits
used to control various configurable functions within the SA-1100. The power manager PLL
configuration register (PPCR) allows the user to change the PLL operating frequency. The power
manager GPIO sleep state register (PGSR) is used to program the value loaded onto GPIO outputs
when the SA-1100 transitions into sleep mode. The power manager oscillator status register
(POSR) contains a single bit that indicates whether the 32.768-kHz oscillator has stabilized after a
hardware reset.
9.5.7.1 Power Manager Control Register (PMCR)
Sleep mode is invoked by setting the force bit within the power manager control register (PMCR).
The force bit is automatically cleared upon exiting sleep mode or when a hardware reset occurs.
Writing zero to the force bit has no effect. For reserved bits, writes are ignored and reads return
zero. This register should be protected by programming MMU permissions. The following table
shows the PMCR.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R/W Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R/W Reserved SF
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit Name Description
0 SF Sleep force.
0 - Do not force invocation of sleep mode.
1 - Force invocation of sleep mode.
Note: This bit is cleared on wake-up or a hardware reset.
31..1 — Reserved.