Intel STRONGARM SA-1100 - Manual (Page 364)

16-4 SA-1100 Developer’s Manual
Boundary-Scan Test Interface
16.5.4 HIGHZ (00101)
The HIGHZ instruction connects a 1-bit shift register (the BYPASS register) between TDI and
TDO. When the HIGHZ instruction is loaded into the instruction register, all outputs are placed in
an inactive drive state.
In the CAPTURE-DR state, a logic 0 is captured by the bypass register. In the SHIFT-DR state, test
data is shifted into the bypass register via TDI and out via TDO after a delay of one TCK cycle.
Note that the first bit shifted out will be a zero. The bypass register is not affected in the
UPDATE-DR state.
16.5.5 IDCODE (00110)
The IDCODE instruction connects the device identification register (or ID register) between TDI
and TDO. The ID register is a 32-bit register that allows the manufacturer, part number and version
of a component to be determined through the TAP. When the instruction register is loaded with the
IDCODE instruction, all the boundary-scan cells are placed in their normal (system) mode of
operation.
In the CAPTURE-DR state, the device identification code (specified at the end of this section) is
captured by the ID register. In the SHIFT-DR state, the previously captured device identification
code is shifted out of the ID register via the TDO pin, while data is shifted in via the TDI pin into
the ID register. In the UPDATE-DR state, the ID register is unaffected.
16.5.6 BYPASS (11111)
The BYPASS instruction connects a 1-bit shift register (the BYPASS register) between TDI and
TDO. When the BYPASS instruction is loaded into the instruction register, all the boundary-scan
cells are placed in their normal (system) mode of operation. This instruction has no effect on the
system pins.
In the CAPTURE-DR state, a logic 0 is captured by the bypass register. In the SHIFT-DR state, test
data is shifted into the bypass register via TDI and out via TDO after a delay of one TCK cycle.
Note that the first bit shifted out will be a zero. The bypass register is not affected in the
UPDATE-DR state.