Intel STRONGARM SA-1100 - Manual (Page 22)

1-2 SA-1100 Developer’s Manual
Introduction
Table 1-1. Features of the SA-1100 CPU for AA and EA Parts
• High Performance
— 150 Dhrystone 2.1 MIPS @ 133 MHz
— 220 Dhrystone 2.1 MIPS @ 190 MHz
• Low power (normal mode)†
— <230 mW @1.5 V/133 MHz
— <330 mW @ 1.5 V/200 MHz
• Integrated clock generation
— Internal phase-locked loop (PLL)
— 3.686 MHz oscillator
— 32.768 kHz oscillator
• Power-management features
— Normal (full-on) mode
— Idle (power-down) mode
— Sleep (power-down) mode
• Big and little endian operating modes
• 3.3 V I/O interface
• 208-pin thin quad flat pack (LQFP)††
• 256 mini-ball grid array (mBGA)
• 32-way set-associative caches
— 16 Kbyte instruction cache
— 8 Kbyte write-back data cache
• 32-entry memory-management units
— Maps 4 Kbyte, 8 Kbyte, or 1 Mbyte
• Write buffer
— 8-entry, between 1 and 16 bytes each
• Read buffer
— 4-entry, 1, 4, or 8 words
• Memory bus
— Interfaces to ROM, Flash, SRAM,
and DRAM
— Supports two PCMCIA sockets
† Power dissipation, particularly in idle mode, is strongly dependent on the details of the system design.
†† Package nomenclature has been modified due to industry standardization of packages. LQFP is 1.4mm
thick, thin quad flat pack. Please note that no modification has been made to the package itself.
Table 1-2. Features of the SA-1100 CPU for CA and DA Parts
• High Performance
— 180 Dhrystone 2.1 MIPS @ 160 MHZ
— 250 Dhrystone 2.1 MIPS @ 220 MHz
• Low power (normal mode)†
— <430 mW @ 2.0-V/160-MHz
— <550 mW @ 2.0-V/220-MHz
• Integrated clock generation
— Internal phase-locked loop (PLL)
— 3.686-MHz oscillator
— 32.768-kHz oscillator
• Big and little endian operating modes
• 3.3-V I/O interface
• 208-pin thin quad flat pack (LQFP)††
• 256 mini-ball grid array (mBGA)
• 32-way set-associative caches
— 16 Kbyte instruction cache
— 8 Kbyte write-back data cache
• 32-entry memory-management units
— Maps 4 Kbyte, 8 Kbyte, or 1 Mbyte
• Write buffer
— 8-entry, between 1 and 16 bytes each
• Read buffer
— 4-entry, 1, 4, or 8 words
• Memory bus
— Interfaces to ROM, Flash, SRAM,
and DRAM
— Supports two PCMCIA sockets
† Power dissipation, particularly in idle mode, is strongly dependent on the details of the system design.
†† Package nomenclature has been modified due to industry standardization of packages. LQFP is 1.4mm
thick, thin quad flat pack. Please note that no modification has been made to the package itself.