Intel STRONGARM SA-1100 - Manual (Page 231)

SA-1100 Developer’s Manual 11-81
Peripheral Control Module
11.9.1.5 Data Field
The data field can be any length that is a multiple of 8 bits, including zero. The user determines the
data field length according to the application requirements and transmission characteristics of the
target system. Usually a length is selected that maximizes the amount of data that can be
transmitted per frame to allow the CRC checker to consistently detect all errors during
transmission. Note that serial port 1 does not support residue coding found in common SCCs; all
data fields must be a multiple of 8 bits. If a data field that is not a multiple of 8 bits is received, an
abort is signalled and the end of frame tag is set within the receive FIFO. Also note that each byte
within the data field is transmitted and received starting with its LSB and ending with its MSB.
11.9.1.6 CRC Field
SDLC uses the established CCITT cyclic redundancy check (CRC) to detect bit errors that occur
during transmission. A 16-bit CRC-CCITT is computed using the address, control, and data fields,
and is included in each frame. A separate CRC generator is implemented in both the transmit and
receive logic. The transmitter calculates a CRC while data is actively transmitted, and places the
16-bit value at the end of each frame before the flag is transmitted. The receiver calculates a CRC
for each received data frame, and compares the calculated CRC to the expected CRC value
contained within the end of each received frame. If the calculated value does not match the
expected value, an interrupt is signalled. The CRC computation logic is preset to all ones before
reception or transmission of each frame. Note that, unlike all other fields within the frame, the
CRC is transmitted and received starting with its MSB and ending with its LSB. The CRC logic
uses the following four-term polynomial in the implementation of its linear feedback shift register.
11.9.1.7 Baud Rate Generation
The baud or bit rate is derived by dividing down the 3.6864-MHz clock generated by the on-chip
PLL. The clock is first divided by a programmable number between 1 and 4096, and then by a
fixed value of 16. The receive baud clock is synchronized with the data steam each time a transition
is detected on the receive data line at a bit’s boundary. For FM0 encoding, zeros and ones are
decoded within the incoming data stream by detecting whether a transition occurs between the
boundaries of a bit time. If the receive line transitions, a zero is decoded; otherwise, a one is
decoded. The baud synchronizer differentiates a transition of the receive line at the bit boundary
from a transition caused by a zero by first establishing the bit boundary during reception of the
string of ones within the flag (01111110). A counter is then used to cause the synchronizer to ignore
transitions that occur during mid-bit. This is accomplished by using the clock produced before the
fixed divide by 16 takes place. This clock is used to increment a counter that is reset at the
boundary of each bit. Transitions that take place at any time before the counter reaches the value 12
(3/4 of a total bit time) are ignored. This function effectively masks a transition, which occurs
during reception of a zero, excluding it from the bit synchronization process. When NRZ encoding
is used, each bit of received data is sampled at its midpoint by using the clock that is generated
before the fixed divide by 16 takes place. A sample rate counter is used that is reset at the boundary
of each bit and is incremented using this clock. When it reaches a value of 8 (halfway through the
bit period), the receive data pin is sampled.
CRC x
( )
X16 X12 X5 1 + + +
( )
=