Intel STRONGARM SA-1100 User Manual

Intel, Strongarm, Sa-1100 microprocessor

Intel

StrongARM

SA-1100

Microprocessor

Developer’s Manual

August 1999

Order Number:

278088-004

Table of contents

Document Outline

Intel® StrongARM® SA-1100 Microprocessor Developer's Manual
Copyright Page
Contents
Figures
Tables
Introduction 1
- 1.1 Intel® StrongARM® SA-1100 Microprocessor
- 1.2 Overview
- 1.3 Example System
- 1.4 ARM™ Architecture
Functional Description 2
- 2.1 Block Diagram
- 2.2 Inputs/Outputs
- 2.3 Signal Description
- 2.4 Memory Map
ARM™ Implementation Options 3
- 3.1 Big and Little Endian
- 3.2 Exceptions
- 3.3 Coprocessors
Instruction Set 4
- 4.1 Instruction Set
- 4.2 Instruction Timings
Coprocessors 5
- 5.1 Internal Coprocessor Instructions
- 5.2 Coprocessor 15 Definition
Caches, Write Buffer, and Read Buffer 6
- 6.1 Instruction Cache (Icache)
- 6.2 Data Caches (Dcaches)
- 6.3 Write Buffer (WB)
- 6.4 Read Buffer (RB)
Memory-Management Unit (MMU) 7
- 7.1 Overview
  - 7.1.1 MMU Registers
- 7.2 MMU Faults and CPU Aborts
- 7.3 Data Aborts
  - 7.3.1 Cacheable Reads (Linefetches)
  - 7.3.2 Buffered Writes
- 7.4 Interaction of the MMU, Icache, Dcache, and Write Buffer
- 7.5 Mini Data Cache
Clocks 8
- 8.1 SA-1100 Crystal Oscillators
- 8.2 Core Clock Configuration Register
  - 8.2.1 Restrictions on Changing the Core Clock Configuration
- 8.3 Driving SA-1100 Crystal Pins from an External Source
- 8.4 Clocking During Test
System Control Module 9
- 9.1 General-Purpose I/O
- 9.2 Interrupt Controller
  - 9.2.1 Interrupt Controller Register Definitions
  - 9.2.2 Interrupt Controller Register Locations
- 9.3 Real-Time Clock
- 9.4 Operating System Timer
- 9.5 Power Manager
- 9.6 Reset Controller
  - 9.6.1 Reset Controller Registers
    - 9.6.1.1 Reset Controller Software Reset Register (RSRR)
    - 9.6.1.2 Reset Controller Status Register (RCSR)
  - 9.6.2 Reset Controller Register Locations
Memory and PCMCIA Control Module 10
- 10.1 Overview of Operation
- 10.2 Memory Configuration Registers
- 10.3 Dynamic Interface Operation
- 10.4 Static Memory Interface
- 10.5 General Memory BUS Timing
- 10.6 PCMCIA Overview
- 10.7 Initialization of the Memory Interface
  - 10.7.1 Flow of Events After Reset or Exiting Sleep Mode
- 10.8 Alternate Memory Bus Master Mode
Peripheral Control Module 11
- 11.1 Read/Write Interface
- 11.2 Memory Organization
- 11.3 Interrupts
- 11.4 Peripheral Pins
- 11.5 Use of the GPIO Pins for Alternate Functions
- 11.6 DMA Controller
- 11.7 LCD Controller
- 11.8 Serial Port 0 – USB Device Controller
- 11.9 Serial Port 1 – SDLC/UART
- 11.10 Serial Port 2 – Infrared Communications Port (ICP)
- 11.11 Serial Port 3 - UART
- 11.12 Serial Port 4 – MCP / SSP
- 11.13 Peripheral Pin Controller (PPC)
DC Parameters 12
- 12.1 Absolute Maximum Ratings
- 12.2 DC Operating Conditions
- 12.3 Power Supply Voltages and Currents
AC Parameters 13
- 13.1 Test Conditions
- 13.2 Module Considerations
- 13.3 Memory Bus and PCMCIA Signal Timings
- 13.4 LCD Controller Signals
- 13.5 MCP Signals
- 13.6 Timing Parameters
  - 13.6.1 Asynchronous Signal Timing Descriptions
Package and Pinout 14
- 14.1 Mechanical Data and Packaging Information
- 14.2 Mini-Ball Grid Array – (mBGA)
Debug Support 15
- 15.1 Instruction Breakpoint
- 15.2 Data Breakpoint
Boundary-Scan Test Interface 16
- 16.1 Overview
- 16.2 Reset
- 16.3 Pull-Up Resistors
- 16.4 Instruction Register
- 16.5 Public Instructions
- 16.6 Test Data Registers
- 16.7 Boundary-Scan Interface Signals
Register Summary A
3.6864–MHz Oscillator Specifications B
- B.1 Specifications
  - B.1.1 System Specifications
  - B.1.2 Quartz Crystal Specification
32.768–kHz Oscillator Specifications C
- C.1 Specifications
  - C.1.1 System Specifications
  - C.1.2 Quartz Crystal Specification
Internal Test D
- D.1 Test Unit Control Register (TUCR)
Support, Products, and Documentation