Intel STRONGARM SA-1100 - Manual (Page 285)

SA-1100 Developer’s Manual 11-135
Peripheral Control Module
11.11.5 UART Control Register 3
UART control register 3 (UTCR3) contains six different bit fields that control various functions
within the UART.
11.11.5.1 Receiver Enable (RXE)
The receiver enable (RXE) bit is used to enable and disable all UART receive operations. When RXE=1,
the UART receive logic is enabled; when RXE=0, it is disabled. When the receiver is disabled, control of
the RXD3 pin is given to the peripheral pin controller (PPC) so that it may be used for general-purpose
input and output (noninterruptible). See the
Section 11.13, “Peripheral Pin Controller (PPC)” on
page 11-184 for a description of the PPC.
It is required that the user first program all other control bits before setting RXE (even the transmit
bits). If the RXE bit is cleared to zero while the UART is actively receiving data, reception is
stopped immediately and the remaining bits within the receive serial shifter are reset. In addition,
all entries within the receive FIFO are reset (all other control/status/flag bits remain intact).
11.11.5.2 Transmitter Enable (TXE)
The transmitter enable (TXE) bit is used to enable and disable all UART transmit operations. When
TXE=1, UART transmit logic is enabled; when TXE=0, it is disabled. When the transmitter is disabled,
control of the TXD3 pin is given to the peripheral pin controller (PPC) for general-purpose input and
output use (noninterruptible). See the
Section 11.13, “Peripheral Pin Controller (PPC)” on
page 11-184 for a description of the PPC.
It is required that the user first program all other control bits before setting TXE (even the receive
bits). If the TXE bit is cleared to zero while the UART is actively transmitting data, transmission is
stopped immediately and the remaining bits within the transmit serial shifter are reset. In addition,
all entries within the transmit FIFO are reset (all other control/status/flag bits remain intact).
11.11.5.3 Break (BRK)
The break (BRK) control bit is used to continuously transmit a break by forcing the transmit pin
(TXD3) low. When the BRK bit is set, the transmit pin is forced low immediately. If the transmitter is
actively transmitting data, the remaining bits in the serial shifter continue to be shifted out, but the bits
are ignored (not placed on the transmit pin). Asserting BRK also prevents the transmit logic from
fetching any additional data from the transmit FIFO once the shifter is empty. The transmit pin
remains low until the BRK bit is cleared, or alternatively, if the transmitter is disabled (TXE=0, or a
reset occurs). Once BRK is negated, transmission starts again. The user must ensure that the BRK bit
is asserted long enough to cause the off-chip receiver to detect the break condition. The user should
also check the transmitter busy (TBY) flag in the status register to ensure that no bits remain in the
transmitter’s serial shifter before negating BRK. TBY is asserted as long as the transmitter is actively
clocking data through the serial shifter. Once the TBY bit becomes zero, the BRK bit can be negated,
and data is once again fetched from the transmit FIFO. Break does not affect the receive portion of the
FIFO; normal operation on the receive line continues during the signalling of a break.
11.11.5.4 Receive FIFO Interrupt Enable (RIE)
The receive FIFO interrupt enable (RIE) bit is used to mask or enable both the receive FIFO service request
interrupt and receiver idle interrupt. When RIE=0, the interrupts are masked and the receive FIFO service
request (RFS) and receiver idle status (RID) bits are ignored by the interrupt controller. When RIE=1, the
interrupts are enabled and whenever RFS or RID is set (one), an interrupt request is made to the interrupt
controller. Note that programming RIE=0 does not affect the current state of RFS or RID nor the receive
logic’s ability to set and clear these bits; it only blocks the generation of the interrupt request. Also note that
RIE does not affect generation of the receive FIFO DMA request that is asserted whenever RFS=1.