Intel STRONGARM SA-1100 - Manual (Page 142)

10-28 SA-1100 Developer’s Manual
Memory and PCMCIA Control Module
10.6.2 External Logic for PCMCIA Implementation
The SA-1100 requires external logic to complete the PCMCIA socket interface. Figure 10-12 and
Figure 10-13 show general solutions for a one- and two-socket configuration. Figure 10-14 shows
a solution for the voltage-control circuit. These diagrams provide the logical connections necessary
for support of 3 V and 5 V PCMCIA cards as well as hot insertion capability. For dual-voltage
support, level shifting buffers are required for all signals. Hot insertion capability requires that each
socket be electrically isolated from the other. If one or both of these features is not required, then
some of the logic shown in these diagrams may be eliminated.
The pull-ups shown are included for compliance with the PCCARD xxx standard. Low power
systems should remove power from these pull-ups during sleep to avoid unnecessary power
consumption. The CD<2:1> signals have been “ORed” before being provided to the SA-1100. This
signal is then routed into a GPIO pin for interrupt capability. Similarly, RDY/BSY is routed to a
GPIO. The INPACK# signal is not used. In the data bus transceiver control logic, nCE1 should
control the enable for the low byte lane and nCE2 should control the enable for the high byte lane.