Intel STRONGARM SA-1100 - Manual (Page 298)

11-148 SA-1100 Developer’s Manual
Peripheral Control Module
Note that the transmit line is pulled low any time data is not being driven onto the pin. The
UCB1100 and UCB1200 have a programming option that allows them to either tristate or drive the
receive line low when data is not being driven onto RXD4. As shown in
Figure 11-32 , MCP frames
occur back-to-back. The SFRM pin is pulsed high during the last clock (128th) of the frame to
indicate the start of a new frame the following SCLK period. Values contained within the transmit
FIFOs are loaded to the shift register on the rising edge of SFRM.
11.12.1.2 Audio and Telecom Sample Rates and Data Transfer
The UCB1100 and UCB1200 contain both an audio and telecom codec with sample rates that can
be individually programmed, and are derived from the programmed serial clock (SCLK) that is
supplied by the MCP. For the audio codec, the sample rate is derived by dividing the serial clock
first by a fixed value of 32, then by a value from 6 to 127. The same is true for the telecom codec,
except that the programmable divisor ranges from 16 to 127. The codec and the MCP both contain
an audio and a telecom sample rate counter. These counters are used to achieve conversion rate
synchronization between the codec and MCP so that data may be coherently transferred between
the MCP and the codec. For the remainder of this description, references made to the audio codec
also apply to the telecom portion of the codec and MCP.
Before enabling the audio codec, the audio sample rate counters within the codec and MCP must
programmed with the same divisor value so that they have the same clock rate. The codec’s audio
sample rate divisor is programmed by issuing a control register write transfer, and the MCP’s
divisor is programmed using the CPU by writing to the MCP’s control register. Both the MCP and
the codec’s audio counters are reloaded with the programmed modulus value any time the audio
portion of the codec is enabled (which is also accomplished by performing a control register write
transfer), or whenever the sample rate counters reach zero.
The MCP and the audio codec decrement their counters in lock-step with one another, both starting
on the occurrence of the first SFRM pulse after the audio codec is enabled. Samples/conversions
are made each time the audio codec’s counter reaches zero.
Figure 11-33 shows the timing of the
audio codec enable and decrements of the MCP and audio codec’s sample counter.
Figure 11-33. MPC/Codec Sampling Counter Synchronization
In the preceding figure, “Ena,” within the data frame on TXD4, represents a control register write to the
codec to enable the input portion of the audio codec. The register is updated with the write at the end of
subframe and the audio enable signal within the codec goes high. Both the MCP and codec’s audio
sample rate counters then start to decrement on the next SFRM pulse. In the example, a divisor value of
12 is used, causing the counter to decrement to zero after 384 (32*12=384) SCLK cycles occur.
Subframe 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
SFRM
TXD4 Ena Dis
Audio Ena
Counters 12....12 12.11.10.9.8.7.6.5.4.3.2.1 12.11.10.9.8.7.6.5.4.3.2.1 12.11.10.9.8.7.6 12...................12
Samp/Conv