Intel STRONGARM SA-1100 - Manual (Page 200)

11-50 SA-1100 Developer’s Manual
Peripheral Control Module
11.7.12 LCD Controller Register Locations
Table 11-9 shows the registers associated with the LCD controller and the physical addresses used
to access them.
Figure 11-34 to Figure 11-38 describe the LCD controller timing parameters.
Table 11-9. LCD Controller Control, DMA, and Status Register Locations
Address Name Description
0hB010 0000 LCCR0 LCD controller control register 0
0hB010 0004 LCSR LCD controller status register 1
0hB010 0008 – 0h B010 000C — Reserved
0hB010 0010 DBAR1 DMA channel 1 base address register
0hB010 0014 DCAR1 DMA channel 1 current address register
0hB010 0018 DBAR2 DMA channel 2 base address register
0hB010 001C DCAR2 DMA channel 2 current address register
0hB010 0020 LCCR1 LCD controller control register 1
0hB010 0024 LCCR2 LCD controller control register 2
0hB010 0028 LCCR3 LCD controller control register 3
0hB010 002C – 0hB010 FFFF — Reserved